Open side-bar Menu
 Real Talk

Archive for November 5th, 2012

Ascent Lint Rule of the Month: ZERO_REP

Monday, November 5th, 2012

Ascent Lint can check your RTL design against hundreds of rules and coding checks.  The problem is, how can I tell people about them?  You’ve got more important things to  do than to slog though all the details of what Ascent Lint can do for you and your HDL design. Then it occurred to me that maybe the best way to talk about these rules is one at a time.  That way, you get some useful information, and you and I can both get to our pressing list of t0-dos. I want to discuss our first Lint Rule of the Month, ZERO_REP.

In Verilog, a replication concatenate expression { C { expr } } means that the value of expr is copied C times and concatenated together to produce the result.  For understandable reasons, the first version of the Verilog simulator made the reasonable assumption that any logic expression will have some length greater than zero, so it evaluates { 0 { expr} } to be 1’b0. Since then, the Verilog language been standardized in IEEE-1364, commonly referred to as the Language Reference Manual, or LRM for short. The committee that determined how things should work observed that zero copies of an expression ought to result in an expression with zero length, provided that it was then concatenated with something else of some non-zero length, again to avoid the problem of a zero length value by the time it is assigned to something else.

(more…)

CST Webinar Series
S2C: FPGA Base prototyping- Download white paper



Internet Business Systems © 2016 Internet Business Systems, Inc.
595 Millich Dr., Suite 216, Campbell, CA 95008
+1 (408)-337-6870 — Contact Us, or visit our other sites:
TechJobsCafe - Technical Jobs and Resumes EDACafe - Electronic Design Automation GISCafe - Geographical Information Services  MCADCafe - Mechanical Design and Engineering ShareCG - Share Computer Graphic (CG) Animation, 3D Art and 3D Models
  Privacy Policy