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Archive for November, 2012

Real Intent Has Excellent EDSFair 2012 Exhibition

Monday, November 19th, 2012

Real Intent showcased and discussed its two product families – Ascent™ for early functional verification before synthesis; and Meridian™ for advanced sign-off verification for CDC and timing constraints, at the EDSFair in Yokohama City in Japan, Nov. 14-16. Our country Manager at Real Intent KK, Yasuo Torisawa, and Senior Application Engineering Manager, Kazutaka Kanda, met with a large number of visitors at its booth.  The reception to Real Intent’s best-in-class products was excellent and many new business discussions were started.
Here below are some pictures taken at the Real Intent booth.

Ascent Lint Rule of the Month: ZERO_REP

Monday, November 5th, 2012

Ascent Lint can check your RTL design against hundreds of rules and coding checks.  The problem is, how can I tell people about them?  You’ve got more important things to  do than to slog though all the details of what Ascent Lint can do for you and your HDL design. Then it occurred to me that maybe the best way to talk about these rules is one at a time.  That way, you get some useful information, and you and I can both get to our pressing list of t0-dos. I want to discuss our first Lint Rule of the Month, ZERO_REP.

In Verilog, a replication concatenate expression { C { expr } } means that the value of expr is copied C times and concatenated together to produce the result.  For understandable reasons, the first version of the Verilog simulator made the reasonable assumption that any logic expression will have some length greater than zero, so it evaluates { 0 { expr} } to be 1’b0. Since then, the Verilog language been standardized in IEEE-1364, commonly referred to as the Language Reference Manual, or LRM for short. The committee that determined how things should work observed that zero copies of an expression ought to result in an expression with zero length, provided that it was then concatenated with something else of some non-zero length, again to avoid the problem of a zero length value by the time it is assigned to something else.


DownStream: Solutions for Post Processing PCB Designs
Verific: SystemVerilog & VHDL Parsers
TrueCircuits: UltraPLL

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