Archive for October, 2012
In late September, I blogged about the results of our DAC survey on CDC bugs, X propagation, constraints. Now for those of you who don’t know what CDC means, it is an acronym for Clock Domain Crossing. Lots of different clock domains are used because of the integration of different blocks and IP in modern SoCs. Not only must CDC be analysed, it is now becoming a sign-off requirement.
In our survey it showed that 62% of the respondents said that CDC bugs resulted in late ECOs. These bugs are affecting design schedules and design teams need to do thorough CDC verification. What are the other 28% doing? Some design teams tell us that their design methodology is immune to CDC issues. This is not typical for fabless semi design teams.
Chip Design Magazine has also been running a poll: Have you had CDC bugs slip through resulting in late ECOs or chip respins? on their web-site. If you go to ChipDesignMag.com and scroll half-down the page and on the left side you will see this:
I have been monitoring this poll for a while and there has not been a lot of recent activity. Feel free to go to the ChipDesignMag.com web-site and scroll down to cast your vote. Here are the results so far: (more…)