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Archive for September 6th, 2012

Video: Ascent IIV Finds RTL Functional Bugs that Simulation Can Miss

Thursday, September 6th, 2012

Chris Morrison, Chief Architect at Real Intent discusses the differences that set the Implied Intent Verification (IIV) tool apart from lint and simulation. He highlights the positive impact on RTL designs that have even 99% testbench coverage. This interview took play in July 2012.

Chris Morrison was employee #2 at Real Intent.  He brings over 25 years of EDA software engineering experience to the team.  Previous to Real Intent he led the engineering development of clock tree generation and placement based optimization tools at Cadence Design Systems.  Prior to that he worked at Viewlogic Systems.  His PhD is from the University of Colorado and BSEE is from Yale University.  Chris has been awarded six patents in the areas of IC design and verification.

DownStream: Solutions for Post Processing PCB Designs
Verific: SystemVerilog & VHDL Parsers
TrueCircuits: UltraPLL



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