Graham is VP of Marketing at Real Intent. He has over 20 years experience in the design automation industry. He has founded startups, brought Nassda to an IPO and previously was Sales and Marketing Director at Internet Business Systems, a web portal company. Graham has a Bachelor of Computer … More »
Verification challenges require surgical precision
August 23rd, 2012 by Graham Bell
Pranav Ashar, CTO at Real Intent, discusses how verification challenges require more than simulation and timing analysis.
Design companies have continued to buy functional verification tools through the recent downturn and the prediction is that verification spending will continue to rise. While this is good news for EDA companies, it is also an indicator of the industry’s challenge in containing the verification problem as design complexity continues to rise in terms of the number of transistors and the system-level functionality on a chip.
The common experience is that newer chips have additional failure modes that were not issues before. For example, approximately 85% of the designs today contain more than one clock domain. This is necessitated by a combination of clock-skew considerations as well as the diverse clocking requirements of system-level components on a chip. As a result, chip failures arising from improperly designed clock-domain crossings have become increasingly common.
The repercussions of clock-crossing errors are going to be very visible in large SOCs with numerous asynchronous interfaces and expensive tapeouts.. These new failure modes also impact productivity and ROI on much smaller designs implemented with FPGAs. In other words, the impact is universal across chip sizes, styles and application domains. One of our first customers was, in fact, an FPGA design house. They began using specialized clock-domain verification after discovering numerous interface-related failures in the field and further discovering that these failures were very difficult to reproduce, even in a lab environment. They said that the manifestation of some of the failure symptoms depended on the specific batch of FPGAs received from the fab.