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Archive for August, 2012

When to Retool the Front-End Design Flow?

Thursday, August 30th, 2012

The following blog entry was written by Rick Eram, Director of Field and Sales Operations at Real Intent

I work with many design teams who are trying to find an optimal time point for updating and retooling their front-end design flow.  The decision is not as easy as you might think.  The various managers I meet struggle with this question, since it requires careful analysis of the existing flow, identifying any bottlenecks, and a detailed understanding of the current engineering design cost compared to a replacement toolset.  Managers also have to understand the team interactions around the world, their deliverables and responsibilities, and how designers work within each functional group.  And the switching cost must be quantified in hard numbers.

In the back-end world of circuit netlists and layouts, the decision to retool is simpler since the move to a new silicon technology node typically dictates when to change.  The benefits are obvious and much easier to quantify.  Metrics for run time, capacity, accuracy, and ease of achieving timing closure makes the job of understanding and analyzing the cost of current versus new tools much simpler to understand, quantify, and justify.  If these performance metrics in the current tool-set are degrading significantly because of greater design complexity, and the impact of multiple operating modes and statistical effects, the design team will not be successful.  A change is clearly needed.

So, how does a manager determine when to retool the front-end design flow and maximize efficiency?  Are current tools costing way too much of engineering time and not as efficient as they once were?  What is the real switching cost?  And what about the impact on verification?  Since verification is more and more intertwined with actual RTL design, a decision about a tool change must take that into account. (more…)

Verification challenges require surgical precision

Thursday, August 23rd, 2012

Pranav Ashar, CTO at Real Intent, discusses how verification challenges require more than simulation and timing analysis.

Design companies have continued to buy functional verification tools through the recent downturn and the prediction is that verification spending will continue to rise. While this is good news for EDA companies, it is also an indicator of the industry’s challenge in containing the verification problem as design complexity continues to rise in terms of the number of transistors and the system-level functionality on a chip.


How To Article: Verifying complex clock and reset regimes in modern chips

Thursday, August 16th, 2012

The following was originally published in EDN as an IC Design Center How-To article on Jan. 25, 2011.   It provides a thorough treatment of verifying complex clock and reset regimes, including examples of silicon re-spins caused by clock and reset related failures, and the necessary scalable solutions to sign-off a design. (more…)

X-Verification: What Happens When Unknowns Propagate Through Your Design

Thursday, August 9th, 2012

This article is an update to Lisa Pipers original posting from April 2011: X-verification: Conquering the “Unknown”

SoCs today are highly integrated, employing many disparate types of IP, running at different clock rates with different power requirements. Understanding the new failure modes that arise from confluences of all these complications, as well as how to prevent them and achieve sign-off, is important. While the issue of handling “X’s” in verification has always been there, it has become more exasperated by low power applications that routinely turn off sections of chips, generating “unknowns”.

Lisa introduces the topic of X-Verification in her DVCon 2012 video interview:


Video: “Issues and Struggles in SOC Design Verification”, Dr. Roger Hughes

Thursday, August 2nd, 2012

Dr. Roger Hughes, Sr. Application Engineer at Real Intent speaks with Graham Bell about the current verification challenges for complex SOCs.  This interview took place at the Real Intent DAC 2012 booth in early June.

Roger is a renowned international expert in formal verification technologies and has over 20 years experience in the EDA industry working both at start-up companies in lead engineering roles and publicly traded companies in managing and directing technical product development. He obtained his Electronic Engineering degree at University of Wales, Swansea and his Masters in Digital Systems and his Ph.D in Electronic Engineering at Brunel University, UK. He has published over 70 papers. (more…)

S2C: FPGA Base prototyping- Download white paper

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