Graham is VP of Marketing at Real Intent. He has over 20 years experience in the design automation industry. He has founded startups, brought Nassda to an IPO and previously was Sales and Marketing Director at Internet Business Systems, a web portal company. Graham has a Bachelor of Computer … More »
How is Verification Complexity Changing, and What is the Impact on Sign-off?
July 19th, 2012 by Graham Bell
I had the pleasure of speaking with Pranav Ashar, CTO at Real Intent, in the recorded video below, about how verification complexity is changing in new designs and how that is impacting design sign-off.
Dr. Ashar makes it clear scale complexity is not going away. High-end SOCs today, easily go beyond 100M logic gates and we will see further CMOS silicon technology-shrinks, so bigger designs are forthcoming. With the adoption of the SOC paradigm however, chips have evolved into true systems with diverse components integrated together into one design.
The elephant in the in the room that design teams are now realizing, is that the tremendous effort to create designs with aggressive performance and power goals has consequences for verification. There are now first-order requirements that are not met by the nominal functional verification and timing analysis flows.
Dr. Pranav Ashar brings two decades of EDA expertise to Real Intent. Pranav received his M.S. and Ph.D. in EECS with emphasis on EDA from the University of California, Berkeley in 1989 and 1991, respectively. He then joined NEC Labs in Princeton, NJ where he developed a number of EDA technologies that have influenced the industry. Pranav has authored about 70 publications in refereed conferences and journals with approximately 800 citations, and co-authored a book titled “Sequential Logic Synthesis”. He has 35 patents granted and pending, many of which have been licensed or part of business enablement. Pranav was an adjunct faculty in the CSEE department at Columbia University where he has taught graduate and undergraduate courses on VLSI design automation, VLSI Verification, and VLSI design.