I had the pleasure of speaking with Pranav Ashar, CTO at Real Intent, in the recorded video below, about how verification complexity is changing in new designs and how that is impacting design sign-off.
Dr. Ashar makes it clear scale complexity is not going away. High-end SOCs today, easily go beyond 100M logic gates and we will see further CMOS silicon technology-shrinks, so bigger designs are forthcoming. With the adoption of the SOC paradigm however, chips have evolved into true systems with diverse components integrated together into one design.
The elephant in the in the room that design teams are now realizing, is that the tremendous effort to create designs with aggressive performance and power goals has consequences for verification. There are now first-order requirements that are not met by the nominal functional verification and timing analysis flows.