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Archive for July, 2012

Video: What is Driving Lint Usage in Complex SOCs?

Thursday, July 26th, 2012

A lint tool is a design and coding guideline checker for HDL code and confirms that  it is ‘clean’ and ready for the design tool chain.  The rules used in a lint tool capture years of experience and typically come from industry standards such as the Reuse Methodology Manual (RMM), and the IP reuse guidelines from STARC.

Besides helping to enforce some appropriate naming schemes, they evaluate design and coding deficiencies that impact simulation, synthesis, test, performance and RTL/gate-level sign-off.  Some of the common RTL lint rules include:

  • Unsynthesizable constructs
  • Unintentional latches
  • Unused declarations
  • Multiply driven and undriven signals
  • Race conditions
  • Incorrect usage of blocking and non-blocking assignments
  • Incomplete assignments in subroutines
  • Case statement style issues
  • Set and reset conflicts
  • Out of range indexing


How is Verification Complexity Changing, and What is the Impact on Sign-off?

Thursday, July 19th, 2012

I had the pleasure of speaking with Pranav Ashar, CTO at Real Intent, in the recorded video below, about how verification complexity is changing in new designs and how that is impacting design sign-off.

Dr. Ashar makes it clear scale complexity is not going away.  High-end SOCs today, easily go beyond 100M logic gates and we will see further CMOS silicon technology-shrinks, so bigger designs are forthcoming.  With the adoption of the SOC paradigm however, chips have evolved into true systems with diverse components integrated together into one design.

The elephant in the in the room that design teams are now realizing, is that the tremendous effort to create designs with aggressive performance and power goals has consequences for verification.   There are now first-order requirements that are not met by the nominal functional verification and timing analysis flows.


Foosball, Frosty Beverages and Accelerating Verification Sign-off

Thursday, July 12th, 2012

In this video interview, I talk about the two recent press announcements that just came out about new product releases and growing business momentum, and the fun we were having at the Real Intent booth at DAC in San Francisco, June 4-6.

Here you can see the Foosball table in action:

A Good Design Tool Needs a Great Beginning

Tuesday, July 3rd, 2012

The following blog entry was written by Rick Eram, Director of Field and Sales Operations at Real Intent

Designing an excellent EDA tool takes a great deal of understanding from several different viewpoints.  First the tool designers must understand the actual engineering problem they are trying to solve.  Second, they must understand the end-user design needs and satisfy those in the tool.  Third the results have to be meaningful and consistent with the user’s existing design flow and ideally do not make it harder for designs to be signed off by engineers and their managers.

Software developers spend years refining their products to meet market demands.  The first solution out of the box usually gets the need part right, but can miss on the meaningfulness of the results and presentation of information, as well as ease of use. For example, one of the RTL linting solutions in the marketplace started out as a generic checker over 10 years ago.  A decade later, many hours of unnecessary debugging time is lost every day the tool is invoked because of the overhead due to checking and waiving erroneous messages.  The reason for this misalignment of the customer needs lies solely on the way the tool was designed from the start.


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