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Archive for August, 2011

A Quick History of Clock Domain Crossing (CDC) Verification

Tuesday, August 2nd, 2011

The last decade has seen a sea change in integrated circuit design and verification. Around the year 2000, the Intel Pentium 4 had 42 Million transistors and was built on a 180 nm process, with CPU and interfaces built on different chips. A mere ten years later, Intel’s cloud server, Westmere EX, has 2.6 Billion transistors and was built on a 32nm process. It has 10 64-bit x86 CPUs, graphics, DDRs, virtualization, QPI, L3 Cache, a whole system on the same chip. It is mindboggling to think about the increase of complexity in IC design and verification in just a decade.

Electronic Design Automation (EDA) is a key enabler for the advance of IC/SoC designs. The advances in EDA tools parallel, as much as possible, the advances in IC design and verification. The development of Clock Domain Crossing (CDC) verification is a good example of this advancement.

In 2001, Cliff Cummings published a paper at SNUG called “Synthesis and Scripting Techniques for Designing Multi-asynchronous Clock Domains” ¹. In the paper, he talked about various asynchronous design techniques such as passing signals from fast to slow clock domains, passing multiple control signals, synchronizing datapaths by using handshakes and FIFOs. Cliff also proposed a CDC design methodology by adopting naming conventions and adhering to certain design partitioning principles.  In the paper, Cliff also discussed the impact of implementing asynchronous designs using synthesis and static timing analysis. Back then, Cliff was unaware of any CDC tools in the market. It was the era of simple CDC designs with less than 5 clock domains and manual review for CDC verification.

Things changed pretty quickly. In 2002, the first-generation CDC tools came to the market. Real Intent’s Verix CIV (Clock Intent Verification) was one of the pioneers in this field. The characteristic of the first generation tools was that they used structural analysis techniques to see if proper synchronization is in place and if there are unsafe CDC structures. While structural analysis alone was not sufficient to prove that all the asynchronous transfer protocols are safe, it was a step in the right direction and provided high value over manual review.

The second-generation CDC tools came around 2007, including Real Intent’s Meridian™ CDC.  These tools represented an advance in CDC verification technology by incorporating multiple verification techniques in addition to structural analysis. Formal analysis became an integral part of the solution in order to check for things such as data stability, pulse width, gray encoding and glitch potential. The tools also provided a simulation library and monitors so that users can perform CDC verification by injecting metastability effects during simulation and catching CDC violations using monitors. This advancement was necessitated by the number of bugs that slipped through to silicon due to clocking issues. According to Collett International and Farwest Research Group’s surveys conducted in 2002, 2004 and 2007, about 20% of chip re-spins were caused by clocking issues. As a result, functional CDC verification using formal analysis and simulation have become must-have techniques in the CDC verification flow.

Recognizing the change in CDC landscape, Cliff Cummings wrote a follow-up paper entitled “Clock Domain Crossing (CDC) Design & Verification Techniques Using SystemVerilog” ², which won the 1st place award at SNUG 2008.  In this paper, Cliff provided a detailed discussion on problems and solutions in CDC design and verification, and in particular, he mentioned that the industry by then has identified these types of design techniques as clock domain crossing techniques. By 2008, CDC had become a known acronym in the industry and the problem space is also more or less well understood.

However well understood the problem may be, doesn’t mean it is completely solved. Advancement in design size and complexity has created additional requirements in CDC verification in recent years in the areas of performance and capacity. The second-generation tools, though functionally comprehensive, do not meet the needs of technology leaders who are designing multi-million-gate SoC designs with complex clocking architectures. To serve these companies, Real Intent released Meridian CDC 3.0 in 2010, with a focus on capacity and speed so as to enable CDC sign-off. With Meridian CDC 3.0, it is possible to verify over 100 Million gate flat full-chip designs with over 100 clock domains without having to break the design into smaller pieces for CDC verification. This translates into major productivity gains for the design team, and also eliminates the chance of bugs slipping through when stitching results together from sub-blocks. The ability to process a whole 100 Million gate design flat represents a significant improvement over earlier and other solutions.

The past 10 years have seen many changes in CDC design and verification. From a couple of asynchronous clock domains to well over 100 asynchronous clocks, from manual review to the 3rd generation CDC tools, and the trend is set to continue. Real Intent is a veteran and leader in the field of CDC verification, and will continue to serve the needs of design teams who are pushing the limit of today’s SoC designs as they approach one billion gates.


¹ Cliff Cummings, “Synthesis and Scripting Techniques for Designing Multi-asynchronous Clock Domains”,, SNUG-2001.

² Cliff Cummings, “Clock Domain Crossing (CDC) Design & Verification Techniques Using SystemVerilog”,, SNUG-2008.

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