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Archive for July, 2011

Hardware-Assisted Verification and the Animal Kingdom

Tuesday, July 26th, 2011

A senior executive of one of the big three EDA vendors was once quoted as saying:  “An emulator you used four years ago, you can use as a bookend, but not much else.  Or, you can throw it over the side of a boat and use it to grow coral.”

While we’ve chuckled over this comment for years, we think a better analogy comes from another part of the animal kingdom and it goes something like this:  Traditional hardware emulators are a lot like the dinosaurs that roamed the earth for 160 million years.  Both are now extinct, the latter wiped out at the end of the Mesozoic Era.  The former, wiped out by hardware-assisted verification platforms designed and implemented with the largest commercial FPGAs that are as fast and sleek as a Gazelle.

Dinosaurs were dominant terrestrial vertebrates, a term that sounds slow, plodding and ponderous, not at all unlike the description of early hardware emulators.

At their introduction in the 1980s, emulators were considered revolutionary and a bold feat of engineering marvel.  The high cost of ownership, however, limited adoption to big companies with large budgets and complex design problems.  Further, a traditional emulator’s maximum speed was about one megahertz (MHz), slow even then.  They were also criticized for being difficult to set up, wasting time and resources.  A common refrain in those early days was the excessive time to emulation.

Dinosaurs are known to have laid eggs.  Hmmm.

As we compare the latest generation of hardware emulation systems to the impressive gazelle, it’s easy to understand why they are changing designers’ perception of this market segment.  They perform at significantly faster speeds, are notably dexterous in their design verification deployment, and drastically more cost effective.

Gazelles are reputed to be swift animals.  In fact, some are able to maintain speeds as high as 50 miles per hour for extended periods of time.  Today’s emulation systems are equally swift –– some clock in at 10 megahertz (MHz) on a 40-million gate design.

These new functional verification engines have a small footprint and are light weight, saving space, power and infrastructure costs, and execute at speeds of several megahertz even in transaction-based co-emulation.  Their debugging capabilities are similar to those of the beloved HDL simulator.  Even more attractive is their pricing –– they sell for a fraction of the cost of older generations of emulators.  They can be used by the embedded software team and hardware designers for hardware/software co-verification, and increasingly are used as a solution to an event-based simulator’s runtime problems.

The gazelle is appreciated for being both nimble and graceful, and does not lay eggs.

Experts tell us we can learn much from the Animal Kingdom.  We’ve learned enough to be able to compare and contrast the characteristics of chip verification tools to two venerated animals.  As we’ve shown, traditional emulators have gone the way of the Dinosaur while today’s fast emulation systems are emulating the characteristics of a Gazelle.

Advanced Sign-off…It’s Trending!

Wednesday, July 13th, 2011

DAC. Whether you love it or not, it is a fantastic opportunity to have quality meetings with design and verification engineers from all over the world. No other event brings so many engineers and engineering managers to one place, where important new trends, technologies, challenges and solutions can be discussed and debated.

With double-digit increases in attendance in all categories, DAC 2011 in San Diego was a success. Floor traffic was high, our suites were booked, conversations with designers were productive, and the iPad drawing prizes were flying off the shelves in every booth!

DAC doesn’t just represent an opportunity to tell attendees what solutions we have to offer. More importantly, it is a great opportunity to learn from designers and verification engineers what they think is important, what trends they are noticing, and what they are looking toward in the future.

While much of this discussion in anecdotal, one useful way we gather trend data at Real Intent is through our attendee survey form. Hundreds of visitors to the Real Intent booth completed a survey to report their challenges, attitudes toward different topics, and what keeps them up at night. By aggregating this data we can see some important trends.

One new question we collected data for was the attendees’ plans to adopt RTL Sign-off Technologies. (Note that in this graph, the numbers are absolute, not percentages).

Adoption Plans for Verification Technologies

As you can see, many people are already using Lint and CDC tools, although these areas are still growing as they are being driven by design complexity. The newer applications of Constraint Verification and X-Propagation Analysis showed less current usage, and relative to that, significant interest in adoption. In fact, X-Verification in general was one of the hottest topics at DAC this year, with many visitors to our booth inquiring about our new solution, Ascent™ XV.

Another important question we ask attendees is about the number of clock domains they expect in their next design. I’ll show this as a pie graph, and number of responses to this question was 163.

Number of Clock Domains

Compared to previous surveys we have done, the number of clock domains keeps going up, with two-thirds of respondents expecting more than 25, and a significant number expecting more than 100. This trend is obviously driving the strong demand we are seeing for our flagship product, Meridian™ CDC.

While on the subject of CDC, we asked DAC attendees if they have ever had a CDC bug slip through, causing a late-stage ECO or silicon re-spin.

CDC Bugs Slipping Through

There were 94 responses to this question, with nearly two-thirds reporting that they have had a CDC bug slip through. With the complexity of SoCs increasing, as evidenced by number of clock domains, this is clearly fueling more need for CDC Verification tools like Meridian CDC.

It’s not surprising then, to see the answer to the next question: Do you Consider CDC Verification to be a Sign-off Criterion?

Is CDC a Sign-off Criterion?

With 103 responses, an overwhelming majority, 83% of attendees, see CDC Verification as a necessary addition to their sign-off regimen, since CDC bugs cannot be detected by functional simulation or static-timing analysis.

We also surveyed attendees on the issues that they encounter with their current CDC or Lint tool. As we expected, the problem of noisy reports ranks high. This is primarily because the industry-leading Lint tool, and its add-on CDC option, relies on templates and does not ensure a correct design environment set-up. Without a correct set-up, many non-issues are erroneously flagged, resulting in a noisy report with actual CDC bugs being lost in a sea of tens of thousands of warning messages.

Issues with CDC or Lint Tools

Ranking even higher, interestingly, was performance. As SoC designs grow larger, full-chip CDC analysis becomes intractable for all but the fastest and highest-capacity tools. This is an area where Meridian CDC shines, routinely handling designs in excess of 100 Million gates.

Shifting gears to one of the newest and hottest topics at DAC, we asked attendees about their level of concern about functional bugs that are caused by differences in X-Interpretation, and found that it is quite high.

Concern About X Bugs

While X-Propagation hazards are not a new problem, they are growing in significance thanks to increasing design complexity. Not only can X-Propagation problems mask functional bugs in RTL simulation, but they also require painful debugging of mismatches between RTL and gate-level simulation. Out of the 118 responses to this question, only 13% of attendees registered no concern, and a full quarter were “very concerned”. Indeed, the interest level in Ascent XV, Real Intent’s new solution for X-Verification, was extremely high at DAC.

Finally, we asked about the area of Exceptions and Constraints Management, to learn what “pain points” attendees were dealing with.

Pain Points in Exceptions and Constraints Management

Constraints Checking was easily the highest reported “pain point”, with other areas related to constraints and exceptions also being ranked highly. This is clearly an important and growing problem that requires modern tools, such as Real Intent’s PureTime™, to address constraints and exceptions management across full-chip SoC designs.

In summary, DAC offered Real Intent an opportunity to not only tell attendees about our solutions, but to measure the important trends and concerns that designers face today, as well as report them back to you.

I would like to thank every DAC attendee that completed our survey form. To give them even more reason to participate, each attendee who completed the survey was entered into a drawing for an iPad 2. I am happy to announce that the winner of the iPad 2 drawing was Jim Kelly of NVIDIA. Congratulations, Jim!

We look forward to seeing you next year at DAC 2012 in San Francisco!

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