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Craig Cochran, VP of Marketing and Business Development, Real Intent
Craig Cochran, VP of Marketing and Business Development, Real Intent
Craig is a 22-year EDA veteran who has developed markets for many implementation and verification product areas. He was most recently VP of Marketing for ChipVision Design Systems, a startup focused on low-power ESL design. Before that he was VP of Marketing at Jasper Design Automation where he … More »

Learn about Advanced Sign-off Verification at DAC 2011

May 24th, 2011 by Craig Cochran, VP of Marketing and Business Development, Real Intent

If you are coming to DAC 2011 in San Diego, June 6th through 8th, you’ll want to make sure you visit Real Intent in booth #2131 to learn about the latest technology for Advanced Sign-off Verification.

Real Intent will feature its Ascent™ XV solution, the industry’s first and only solution for comprehensive X-verification and sign-off. Ascent XV isolates and eliminates functional bugs that are masked by X (unknown value) propagation in RTL simulation, and reduces gate-level simulation debugging due to mismatches between RTL and gate-level simulation results caused by differing X interpretation.

Also to be featured are the latest advances in Meridian™ CDC, the industry’s flagship Clock Domain Crossing sign-off verification solution, and new capabilities within Ascent Lint, the industry’s fastest and most accurate lint solution, which is complemented by automatic formal checks in Ascent IIV (Implied Intent Verification).

Real Intent will also show Meridian DFT, its Design-for-Test verification solution, and PureTime™, its constraints management solution with glitch-aware exception verification.

And, to learn what solutions will be crucial to verifying the billion-gate designs that are right around the corner, be sure to hear Real Intent CEO Prakash Narain along with other experts from Intel, Broadcom, NVIDIA, Qualcomm and Mindspeed on the DAC technical panel entitled:

“The Billion Dollar Question: How to Verify Billion-Gate Designs”

Wednesday, June 8, 2011 – 4:00 PM to 6:00 PM – Room 33ABC – For details, Click here

Next-generation chips will contain literally billions of gates that need to be verified before committing to silicon. With billions of dollars at stake, the right solution is crucial for verifying designs susceptible to complex failures arising from corner-case confluences of timing and functionality. This panel will debate the merits of emerging solutions for such self-contained verification problems that threaten to subvert the nominal “simulation plus STA” verification flow.


If you’d like to learn how to comprehensively sign-off on your RTL code for X-accuracy, CDC integrity, syntax, semantics, DFT and constraints integrity, then please be sure to book your private meeting with Real Intent’s experts by visiting  Appointments are available Monday through Wednesday, 9 AM to 6 PM, but slots are limited, so register TODAY!


  • Please visit booth #2131 at DAC 2011
  • Complete a short survey at the booth to enter our drawing!

We look forward to seeing you at the show!

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