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Archive for May 16th, 2011

Getting A Jump On DAC

Monday, May 16th, 2011

Real Intent and SpringSoft got a head start on DAC this year when the companies co-hosted a seminar on May 5th that touched on 4 key technology areas related to Advanced Sign-off Verification. In addition to two great user sessions presented by engineering managers at Broadcom and Mindspeed Technologies, sessions by Real Intent covered Clock Domain Crossing (CDC) Sign-off as well as X Verification, while SpringSoft covered SystemVerilog testbenches and testbench verification. If the interest level shown by the audience is any indication, these will be hot topics at DAC 2011 in San Diego!

One great thing about such events is that they give us an opportunity to survey designers on SoC design trends and discover what they think is important in the area of Sign-off. Since they have taken the time to attend the seminar, clearly these designers have more interest in the subject matter than would be indicated in a purely random poll, but it is still very interesting to see what trends we can learn from the survey. Here are results from some of the questions.

As you might imagine, we asked a lot of questions about Clock Domain Crossing. The first was “How Many Clock Domains Will Your Next Design Have?”

Clock Domains Distrubution Chart

As you can see, the results showed that over half of the designers expect to have 25 or more clock domains on their next chip. We continue to see an upward trend with more SoCs having greater than 50 clock domains and some SoCs already in the hundreds. This greatly increasing complexity is fueling the growth of CDC Verification and driving the capacity, performance and comprehensiveness requirements that have compelled more companies to choose Meridian CDC.

We then asked if designers had ever had a CDC-related bug slip through and cause late-stage ECO or a silicon respin.

77% Reported CDC Bugs Slipping Through

Over three-fourths of these designers reported that they have had a CDC Bug slip through. Clearly, CDC Verification has become an imperative, and one of the most important requirements of a CDC Verification solution is comprehensiveness.

Based on this result, the result of the next question was not a surprise. We asked whether designers considered Clock Domain Crossing Verification to be a Sign-off Criterion. No graph is needed for this one, because 100% of the attendees answered Yes.

Since Sign-off requires a solution with the capacity and performance to handle full-chip designs, without producing noisy reports, we surveyed designers on these issues. For this question, we also broadened the poll to include Lint.

Issues with Current CDC or Lint Tool

Clearly, noise is a major issue with many designers’ current tool.  One user at the seminar reported that a CDC bug had caused a respin of a large SoC. He said that the tool he was using on this design (which was not Meridian CDC) did spot the CDC bug, but it was buried in a report containing 30,000 warnings. This elicited a collective groan from the audience, as many had obviously dealt with this issue. The user reported that he got rid of that tool and replaced it with Meridian CDC from Real Intent.

This graph also shows that performance and capacity are major issues. Designers seem more worried about performance today, since some tools are not able to give quick feedback to designers, but we are hearing more and more concern about Capacity as SoC design sizes grow into the 100s of Millions of gates.

Finally, as I mentioned earlier, one of the technical sessions in this seminar was on X Verification. We also surveyed designers about their level of concern for this hazard.

The result shows that most designers were very concerned about bugs slipping through to silicon due to X-Propagation, which can mask functional bugs due to a phenomenon known as X-Optimism. X-Optimism is a coding hazard that occurs when a simulator assigns a known value when the value really should be unknown. Such bugs are highly elusive, and require a comprehensive solution to flag potential hazards and identify X-Optimism bugs when they occur in RTL simulation. Indeed, the session on Ascent XV for X Verification generated a lot interest and excellent questions about how to detect and eliminate X Bugs.

This seminar gave us the opportunity to preview some of our latest technology for designers in Silicon Valley, as well as to sense what concerns they have and what trends we should be aware of. And it also gave us an opportunity to get a jump on DAC, where we will be showing the latest developments in our solutions for Advanced Sign-off Verification.

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