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Archive for May, 2011

Learn about Advanced Sign-off Verification at DAC 2011

Tuesday, May 24th, 2011

If you are coming to DAC 2011 in San Diego, June 6th through 8th, you’ll want to make sure you visit Real Intent in booth #2131 to learn about the latest technology for Advanced Sign-off Verification.

Real Intent will feature its Ascent™ XV solution, the industry’s first and only solution for comprehensive X-verification and sign-off. Ascent XV isolates and eliminates functional bugs that are masked by X (unknown value) propagation in RTL simulation, and reduces gate-level simulation debugging due to mismatches between RTL and gate-level simulation results caused by differing X interpretation.

Also to be featured are the latest advances in Meridian™ CDC, the industry’s flagship Clock Domain Crossing sign-off verification solution, and new capabilities within Ascent Lint, the industry’s fastest and most accurate lint solution, which is complemented by automatic formal checks in Ascent IIV (Implied Intent Verification).

Real Intent will also show Meridian DFT, its Design-for-Test verification solution, and PureTime™, its constraints management solution with glitch-aware exception verification.

And, to learn what solutions will be crucial to verifying the billion-gate designs that are right around the corner, be sure to hear Real Intent CEO Prakash Narain along with other experts from Intel, Broadcom, NVIDIA, Qualcomm and Mindspeed on the DAC technical panel entitled:

“The Billion Dollar Question: How to Verify Billion-Gate Designs”

Wednesday, June 8, 2011 – 4:00 PM to 6:00 PM – Room 33ABC – For details, Click here

Next-generation chips will contain literally billions of gates that need to be verified before committing to silicon. With billions of dollars at stake, the right solution is crucial for verifying designs susceptible to complex failures arising from corner-case confluences of timing and functionality. This panel will debate the merits of emerging solutions for such self-contained verification problems that threaten to subvert the nominal “simulation plus STA” verification flow.


If you’d like to learn how to comprehensively sign-off on your RTL code for X-accuracy, CDC integrity, syntax, semantics, DFT and constraints integrity, then please be sure to book your private meeting with Real Intent’s experts by visiting  Appointments are available Monday through Wednesday, 9 AM to 6 PM, but slots are limited, so register TODAY!


  • Please visit booth #2131 at DAC 2011
  • Complete a short survey at the booth to enter our drawing!

We look forward to seeing you at the show!

Getting A Jump On DAC

Monday, May 16th, 2011

Real Intent and SpringSoft got a head start on DAC this year when the companies co-hosted a seminar on May 5th that touched on 4 key technology areas related to Advanced Sign-off Verification. In addition to two great user sessions presented by engineering managers at Broadcom and Mindspeed Technologies, sessions by Real Intent covered Clock Domain Crossing (CDC) Sign-off as well as X Verification, while SpringSoft covered SystemVerilog testbenches and testbench verification. If the interest level shown by the audience is any indication, these will be hot topics at DAC 2011 in San Diego!

One great thing about such events is that they give us an opportunity to survey designers on SoC design trends and discover what they think is important in the area of Sign-off. Since they have taken the time to attend the seminar, clearly these designers have more interest in the subject matter than would be indicated in a purely random poll, but it is still very interesting to see what trends we can learn from the survey. Here are results from some of the questions.

As you might imagine, we asked a lot of questions about Clock Domain Crossing. The first was “How Many Clock Domains Will Your Next Design Have?”

Clock Domains Distrubution Chart

As you can see, the results showed that over half of the designers expect to have 25 or more clock domains on their next chip. We continue to see an upward trend with more SoCs having greater than 50 clock domains and some SoCs already in the hundreds. This greatly increasing complexity is fueling the growth of CDC Verification and driving the capacity, performance and comprehensiveness requirements that have compelled more companies to choose Meridian CDC.

We then asked if designers had ever had a CDC-related bug slip through and cause late-stage ECO or a silicon respin.

77% Reported CDC Bugs Slipping Through

Over three-fourths of these designers reported that they have had a CDC Bug slip through. Clearly, CDC Verification has become an imperative, and one of the most important requirements of a CDC Verification solution is comprehensiveness.

Based on this result, the result of the next question was not a surprise. We asked whether designers considered Clock Domain Crossing Verification to be a Sign-off Criterion. No graph is needed for this one, because 100% of the attendees answered Yes.

Since Sign-off requires a solution with the capacity and performance to handle full-chip designs, without producing noisy reports, we surveyed designers on these issues. For this question, we also broadened the poll to include Lint.

Issues with Current CDC or Lint Tool

Clearly, noise is a major issue with many designers’ current tool.  One user at the seminar reported that a CDC bug had caused a respin of a large SoC. He said that the tool he was using on this design (which was not Meridian CDC) did spot the CDC bug, but it was buried in a report containing 30,000 warnings. This elicited a collective groan from the audience, as many had obviously dealt with this issue. The user reported that he got rid of that tool and replaced it with Meridian CDC from Real Intent.

This graph also shows that performance and capacity are major issues. Designers seem more worried about performance today, since some tools are not able to give quick feedback to designers, but we are hearing more and more concern about Capacity as SoC design sizes grow into the 100s of Millions of gates.

Finally, as I mentioned earlier, one of the technical sessions in this seminar was on X Verification. We also surveyed designers about their level of concern for this hazard.

The result shows that most designers were very concerned about bugs slipping through to silicon due to X-Propagation, which can mask functional bugs due to a phenomenon known as X-Optimism. X-Optimism is a coding hazard that occurs when a simulator assigns a known value when the value really should be unknown. Such bugs are highly elusive, and require a comprehensive solution to flag potential hazards and identify X-Optimism bugs when they occur in RTL simulation. Indeed, the session on Ascent XV for X Verification generated a lot interest and excellent questions about how to detect and eliminate X Bugs.

This seminar gave us the opportunity to preview some of our latest technology for designers in Silicon Valley, as well as to sense what concerns they have and what trends we should be aware of. And it also gave us an opportunity to get a jump on DAC, where we will be showing the latest developments in our solutions for Advanced Sign-off Verification.

Don’t Miss Us At DAC 2011 in San Diego! To sign up for a suite presentation and demo, email us today at

Livin’ on a Prayer

Monday, May 9th, 2011

I was driving back from a meeting one day last week with the car radio playing in the background, mulling over the development environment a senior hardware designer had just described.  As you might expect, he depicted a scenario of tightened project cycles, reduced budgets and resources, added features, frustration and loads of late nights and aggravation.  And, of course, bugs, bugs and more bugs in tens of millions of gates.

Then, he said complexity is rising due to the increased use of embedded software.  According to his team’s calculations, the software portion of a system on chip (SoC) is growing at a rate of 140 percent per year, while hardware is expanding about 40 percent year to year.

With all the rolling around in my mind, I barely registered the radio announcer’s voice, but snapped to attention as Bon Jovi began singing:

Whoa, we’re half way there

Whoa oh, livin’ on a prayer

… we’ll make it I swear

Whoa oh, livin’ on a prayer

Whoa, is right!  In an earlier career, Jon Bon Jovi must have been a hardware designer or a verification engineer.  Otherwise, it’s hard to imagine him composing a song about livin’ on a prayer for anything but SoC design.

Verifying hardware design?  An impossible task that, at times, seems to need some celestial intervention or as Bon Jovi intones, prayer.  That’s what it may seem like for the hardware designer I met last week or verification engineer whose job it is to debug the design.

Functional verification is a way to thoroughly debug a design before silicon availability, though exhaustive functional verification using a software simulator is not a viable solution any longer because of its unsatisfactory performance.  Moreover, simulation farms do not address large designs since they require long sequences of tests that consume billions of cycles and cannot be parallelized.

Fortunately, prayers do get answered.  For example, EVE pioneered an approach to hardware-assisted verification that combines traditional emulation and rapid prototyping systems into a single-unified environment for ASIC and SoC debugging and embedded software validation.  And, Real Intent produces automatic verification solutions using innovative formal techniques in an easy to use methodology.

Hardware-based verification platforms are more than just another emulation product because they can be used by hardware designers to verify and debug SoC hardware designs, and embedded software developers to validate SoC embedded software.  The hardware and the embedded software can be debugged concurrently, giving engineering teams two concurrent views of a design, the inner workings of the SoC hardware and the whole embedded software code.  An engineering team can trace and change any of them and monitor the effects.  A hardware bug that effects the embedded software code execution can be traced starting from the embedded software and vice versa.

While Bon Jovi’s lyrics may seem apropos, don’t keep livin’ only on a prayer!  EVE and Real Intent can help.  They will be at the 48th Design Automation Conference next month in San Diego demonstrating their solutions.  Stop by EVE in Booth #2836 and Real Intent in Booth #2131 to learn more.


Special thanks to Bon Jovi.  Livin’ on a Prayer is from the album Slippery when Wet and was released as a single in 1986.

The Journey to CDC Sign-Off

Monday, May 2nd, 2011

On Thursday May 5th, Real Intent and SpringSoft will co-host a seminar addressing “Latest advances in System-on-chip functional verification sign-off”.  One of the topics is, “You are doing CDC verification, but have you achieved CDC sign-off?”, where I will be discussing the history of CDC verification, why it is important to focus on CDC sign-off today, and most importantly, how to achieve CDC sign-off.

Real Intent, as a leader in the space of CDC verification and sign-off, has made great contributions to the field by advancing the technology, as well as in educating the industry on key CDC issues. The Real Talk Blog, over the past year, has featured many articles discussing aspects of CDC verification and sign-off. A few highlights are included here:

CDC (Clock Domain Crossing) Analysis – Is this a misnomer?

Al Joseph, Sr. Application Engineer, wrote about the fact that while the industry was quick to adopt the acronym “CDC”, and many EDA vendors were quick to claim to have a CDC solution, users need to understand what CDC analysis really entails. A Real CDC solution must go far beyond just checking for single-bit and data-bus metastability management. It should also recognize and verify all asynchronous interfaces, support RTL and gate-level netlists, and incorporate structural, formal, and metastability simulation techniques.

Clock Domain Verification Challenges: How Real Intent Is Solving Them

Real Intent CTO, Dr. Pranav Ashar, discussed the mounting challenges facing clock domain crossing verification today, such as the number of signal crossings between asynchronous clock domains, the proliferation of gated clocks, widely disparate and dynamic clock frequencies, reset distribution, timing optimization, etc.  Dr. Ashar also touched upon how Real Intent’s solution addresses these challenges.

Verifying CDC Issues in the Presence of Clocks with Dynamically Changing Frequencies

Vishnu Vimjam, R&D Manager, discussed a unique capability Meridian CDC has in verifying designs with dynamically changing frequencies.  With other solutions, users would have to perform multiple runs to verify the correctness of the design under different frequencies combinations. Using Meridian CDC, however, users can obtain confidence in one run on whether there will be CDC design errors under all possible frequencies. This is the most advanced technique in formal CDC analysis, not a small achievement for Meridian CDC R&D.

What Do You Need to Know for Effective CDC Analysis?

People often underestimate the knowledge required to make the best use of a CDC tool. Sr. Application Engineer Al Joseph outlined all the things a design or verification engineer needs to understand, such as power, testability, quasi-static domains, and mode selection, etc., in order to be the most productive and effective in using a CDC solution.

Is Your CDC Tool of Sign-Off Quality?

With the increase of design size and number of asynchronous clock domains (we have worked with companies with well over 100M gates with 200 asynchronous clock domains), CDC sign-off has become a must-have in the verification sign-off flow. However, not every CDC solution is up to the task of CDC sign-off. Al Joseph, Sr. Application Engineer, wrote about the criteria a CDC tool needs to have in order to enable CDC sign-off.

Top 3 Reasons Why Designers Switch to Meridian CDC from Real Intent

Rick Eram, Director of Sales at Real Intent, has first-hand knowledge of why designers are switching to Meridian CDC after trying out competitors’ products. In short, the main reasons are ease-of-setup, accuracy, performance and coverage. To sum it up, “Doing CDC verification takes a Real CDC tool architected to do the job, not a linter adapted to do CDC work”.

Real Intent has a wealth of knowledge and experience in CDC verification and sign-off. It is our mission to help every design and verification team succeed in achieving CDC sign-off. Come and join us for an informative and fun seminar on May 5th at noon! You can sign up at

I look forward to seeing you there!



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