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Craig Cochran, VP of Marketing and Business Development, Real Intent
Craig Cochran, VP of Marketing and Business Development, Real Intent
Craig is a 22-year EDA veteran who has developed markets for many implementation and verification product areas. He was most recently VP of Marketing for ChipVision Design Systems, a startup focused on low-power ESL design. Before that he was VP of Marketing at Jasper Design Automation where he … More »

Learn About the Latest Advances in Verification Sign-off!

April 5th, 2011 by Craig Cochran, VP of Marketing and Business Development, Real Intent

If you’ve been reading this blog for a while, you know that the industry is seeing big and rapid changes to the Verification Sign-off process. Simulation and Static Timing Analysis are not enough anymore! SoCs today are highly integrated, employing many disparate types of IP, running at different clock rates with different power requirements. Understanding the new failure modes that arise from confluences of all these complications, as well as how to prevent them and achieve sign-off, is important.

Fortunately, Real Intent and SpringSoft have teamed up to offer a free joint seminar at TechMart in Santa Clara on May 5, 2011, titled “The Latest Advances in Verification Sign-off”. The seminar features User Case Studies from Broadcom and Mindspeed, technical sessions on hot topics such as Clock Domain Crossing (CDC) Sign-off, Verification Closure, X-Propagation Verification, and efficient SystemVerilog Testbench development, and a keynote address by Anant Agrawal, Chairman of Verayo, Inc., and a founding member of the SPARC processor team at Sun Microsystems.

Lunch will be served before the keynote, and at the conclusion of the seminar, a very nice gift will be given away in a drawing. Registration is free, so sign up now at

To tempt you a little further, here are abstracts of the technical sessions:

1. You are doing CDC verification, but have you achieved CDC Sign-off?

The trends toward SoC integration and multi-core chip design are driving an exponential increase in the complexity of clock architectures. Functionality that was traditionally distributed among multiple chips is now integrated into a single chip. As a result, the number of clock domains is dramatically increasing, making Clock Domain Crossing (CDC) verification much more complex and an absolute must-have in the verification flow.

However doing CDC verification doesn’t mean you have achieved CDC sign-off. Lint-based CDC analysis, though identifies potential synchronization issues and risky CDC structures, but it does not guarantee that a CDC bug will not slip through to silicon. A systematic CDC verification methodology utilizing different CDC verification technologies in a layered approach needs to be in place in order to achieve CDC robust designs and final CDC sign-off.

This presentation discusses what it means to achieve CDC sign-off, highlights the necessary steps required in a CDC verification methodology that supports CDC sign-off, and uses customer experiences to showcase real life success of such methodology. With this knowledge, you won’t be just doing CDC verification, but achieving CDC sign-off!

2. Don’t Let the X-Bugs Bite: Signing off on X-Verification

Designers spend many, many hours verifying that RTL provides the correct functionality. The expectation is that the gate level simulation produces the same results as the RTL simulation.  X-Propagation is a major cause of differences between gate level and RTL simulation results, and issues are not detected by logical equivalence checkers. Unfortunately, while most X’s are innocuous at the RTL level, they can also mask functional bugs in RTL.  Resolving gate level simulation differences is painful and time consuming because X’s make correlation between the two difficult.  “X-Prop” issues cause costly iterations, painful debug, and sometimes allow X-related functional bugs to slip through.  This presentation explains the common sources of X’s, shows how they can mask real functional issues and why they are difficult to avoid. It also presents a unique practical solution to assist designers in catching X-propagation bugs efficiently at RTL, avoiding iterations that delay sign-off.

3. SystemVerilog Testbench – Innovative Efficiencies for Understanding Your Testbench Behavior

The adoption of SystemVerilog as the core of a modern constrained-random verification environment is ever-increasing.  The automation and sophisticated stimulus and checking capabilities are large reason why.  .  The supporting standards libraries and methodologies that have emerged have made the case for adoption even stronger and all the major simulators now support the language nearly 100%.  A major consideration in verification is debugging and naturally, debug tools have to extend and innovate around the language.  Because the language is object-oriented and more software-like, the standard techniques that have helped with HDL-based debug no longer apply.  For example, event-based signal dumping provides unlimited visibility into the behavior of an HDL-based environment; unfortunately, such straight-forward dumping is not exactly meaningful for SystemVerilog testbenches.  Innovation is necessary.

This seminar will discuss the use of message logging and how to leverage the transactional nature of OVM and UVM-based SystemVerilog testbenches to automatically record transaction data.  We’ll show you how this data can be viewed in a waveform or a sequence diagram to give you a clearer picture of the functional behavior of the testbench.  For more detailed visibility into the testbench execution, we will also discuss emerging technologies that will allow you to dump dynamic object data and view it in innovative ways was well as using this same data to drive other applications such as simulation-free virtual interactive capability.

4. Getting You Closer to Verification Closure

Techniques for Assessing and Improving Your Verification Environment

Today’s leading-edge designs are verified by sophisticated and diverse verification environments, the complexity of which often rivals or exceeds that of the design itself.  Despite advancements in the area of stimulus generation and coverage, existing techniques provide no comprehensive, objective measurement of the quality of your verification environment.  They do not tell you how good your testbench is at propagating the effects of bugs to observable outputs or detecting the presence of bugs.  The result is that decisions about when you are “done” verifying are often based on partial data or “gut feel” assessments.  These shortcomings have led to the development of a new approach, known as Functional Qualification, which provides both an objective measure of the quality of your verification environment and guidance on how to improve it.

This seminar provides background information on mutation-based techniques – the technology behind Functional Qualification – and how they are applied to assess the quality of your verification environment. We’ll discuss the problems and weaknesses that Functional Qualification exposes and how they translate into fixes and improvements that give you more confidence in the effectiveness of your verification efforts.


Get a jump on DAC and find out what’s happening in the world of verification closure and sign-off! Or, if you can’t make it to DAC this year, this is your chance to learn this year’s hot topics. Either way, it’s a great opportunity to learn from the experts for free.

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