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Dr. Roger B. Hughes, Director of Strategic Accounts
Dr. Roger B. Hughes, Director of Strategic Accounts
Dr. Roger B. Hughes is a renowned international expert in formal verification technologies and has over 20 years experience in the EDA industry working both at start-up companies in lead engineering roles and publicly traded companies in managing and directing technical product development. He … More »

The Ascent of Ascent Lint (v1.4 is here!)

March 2nd, 2011 by Dr. Roger B. Hughes, Director of Strategic Accounts

It is quite interesting to see how very difficult-to-find bugs in a synthesized netlist are often the result of simple errors in RTL code.   There are many technologies available to help an RTL designer find coding mistakes, including formal checks and comparatively simple lint checking of the RTL code.  Linting technology has been around a long time, but it is often not used as part of the design flow, and when it is used on an entire chip, the sheer quantity of rule violations reported make any sensible analysis for real problems difficult.  Why?  Because most of the older lint checkers tend to produce very noisy reports where the vast majority of reported violations are of no real concern, yet buried inside several thousand violations are a few that will cause design problems. Older lint checkers also do not have the speed to do checks in real time, while the code is fresh in the designer’s mind and design productivity can be greatly increased on the fly.

One could always argue that any RTL that is non-synthesizable would be reported by the synthesis tool, so why bother to check for it?  The answer is that it is the synthesizable – but incorrect – code that is of greater concern.   Examples of such incorrect code include: assignments where the widths of the operands do not match, case statements with partially enumerated tags and no default tag, arithmetic operations where the bitlengths of an arithmetic operator are not the same. Novice designers and experienced designers alike often make mistakes.  The ability to detect those mistakes is crucial. Here is an example reported by Ascent Lint:

BA_NBA_REG:  filename.v:100  Both blocking and non-blocking assignments to ‘VPipeLine’, other at filename.v:82

Example code at line 100:

        VPipeLine[0] = VDataIn;

Other use at line 82:

            if (i != NSTAGES-2)     VPipeLine[i] <= VPipeLine[i-1];

In the above fragment of Verilog code, it can be seen that a combination of blocking and non-blocking assignments to a register are used in the code.   Clearly, this is a very bad coding style, and it is something that is very difficult for a designer to spot. 

A Lint check of the code can address issues like these very efficiently, provided modern approaches to linting are used. I have seen my customers choose Ascent Lint v1.4 product from Real Intent for several important reasons.

Accuracy (Low Noise)

One of the most important reasons customers choose Ascent Lint is the low noise in the reports. This enables designers to get to a problem very quickly instead of wading through long reports of violations that are of no real concern.  In addition, Ascent Lint 1.4 adds the capability to generate incremental reports, so that only new violations that occurred since the last run are reported to the designer, saving valuable time.


Another very important factor is the speed of Ascent Lint, which is at least 10 times faster than the leading competitive product.  Often, I have seen speeds of 30 times faster than the competition when the run is done on a full chip.  For example, a typical 5M gate design at RTL can easily be linted in just 10 minutes.  The gate level netlist of that same design was run through the linting process in just 5 minutes and with very economical memory consumption of only a few gigabytes.  The beauty of being able to do lint runs so quickly is that any designer working on the code may quickly run Ascent Lint, check the incremental report for any differences, and immediately correct the code while it is still fresh in his or her mind.  This rapid turn-around is simply not possible with the leading competitor’s technology, which forces the designer to run lint overnight and therefore does not help get the code right as it is being written.

Flexibility and Ease of Use

Ascent Lint is very language-flexible. It can accommodate designs in Verilog, SystemVerilog and VHDL as well as designs containing a mixture of all these languages with ease. This enables full-chip Lint checks on designs containing IP from partner companies – a key requirement for some customers. Ascent Lint works at both RTL and gate level, and supports both hierarchical and flattened designs.  It is also easy for any customer to develop separate policy files for RTL and for netlists.

Fast, accurate and flexible linting is crucial to our customers.  Combining speed with informative and accurate reporting makes Ascent Lint v1.4 from Real Intent a definite winner. Call Real Intent to see for yourself!

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