Dr. Pranav Ashar, CTO
Dr. Ashar brings two decades of EDA expertise to Real Intent. He previously worked at NEC Labs (Princeton, NJ) developing formal verification technologies for VLSI design. He authored about 70 papers and co-authored a book titled "Sequential Logic Synthesis." He has 35 patents granted and pending, … More »
Fairs to Remember
February 8th, 2011 by Dr. Pranav Ashar, CTO
EDSFair is a moderate size trade show for EDA companies held in Yokohama near Tokyo. Like DATE and DAC, it is accompanied by a parallel technical conference. It is an opportunity to network with electronic design companies in Tokyo, Osaka, Kyoto and some other nearby high-tech centers.
The show was held on Jan 27 and 28 (Thurs and Friday). The attendance was reasonable. In fact, the show looked quite busy post-lunch on Friday.
Real Intent got great traction at the show by exhibiting its leading edge software: Lint, Automatic Formal Verification, X-Verification, Clock Domain Crossing (CDC) verification, and Timings Constraints Management and Verification. In particular, the presentations on X-Verification and CDC verification were well received with many serious follow-ups. Many attendees from large semiconductor companies seeking better solutions in the front-end verification space were very impressed with Real Intent’s high performance and high capacity Lint and CDC solutions which offer 10X improvement over competition. We got a lot of well qualified leads and it was a great show to start the year for Real Intent.
The next EDSFair will be held in October 2012 in conjunction with a semiconductor industry tradeshow so this was the last one held in the cold Japan winter. But it was well worth remembering.
Notes from Katsuhiko Sakano, General Manager of Real Intent K.K. in Japan
Tokyo University Symposium
The next stop after EDSFair was the “Advanced Design Methodology for VLSI Symposium” at Tokyo University graciously organized by Professor Masahiro Fujita. It was our privilege to participate. Tokyo University is a leading university in Japan and Prof. Fujita is a distinguished researcher in electronic design.
The symposium brought together in one forum Real Intent with NextOp and SpringSoft. In my opinion, these three companies are the thought leaders today in advancing verification technology for the next generation of chips.
NextOp presented its novel technology that finally makes available the automatic generation of assertions and functional coverage. SpringSoft presented new technologies for fast debug and verification closure. One of the ideas they presented had to do with mining the simulation output database in interesting ways for faster debug.
Real Intent gave the audience an intuition and solutions for two verification problems that have become critical bottlenecks in the design flow: (1) the problem of X’s in simulation, and (2) the problem of verifying the humongous number of asynchronous interfaces on today’s chips.
The program was led by a keynote by Maxeler Technologies on industrial-strength high-performance computing with an FPGA-based platform developed by the company.
All in all, the symposium was a very satisfying technical program that covered the state-of-art in high-end design, specification, implementation verification and debug.
The audience consisted of faculty, students and electronic design professionals from local companies. Some of the companies in the audience were large design houses like Hitachi, Toshiba and Fujitsu as well as a number of smaller companies providing verification services, engineering recruitment and sales distribution. It was an excellent opportunity to network with the local professionals in terms of understanding their verification needs and projecting Real Intent as a key provider of enabling technologies for the verification of next-generation chips.
The symposium finished on a high note with a drawing for an iPad. Appropriately, it was won by a student of Prof. Fujita’s.