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Archive for February, 2011

Foundation for Success

Monday, February 21st, 2011

Real Intent has seen much success in the last few years despite the tough economic conditions facing the semiconductor and EDA (electronic design automation) industries during the recession. Real Intent’s revenue was up over 80% in 2010 and the size of the Real Intent team grew by 35% (and yes we are still looking for talented individuals to join our team!). This stellar growth was built upon a solid foundation. When talking to Russ Henke, contributing editor for EDACafe’s EDA Weekly, Prakash Narain, CEO of Real Intent, detailed the reasons for the success Real Intent had:

“It pays to learn hard lessons in life early. In the early years of Real Intent when we were focusing on harnessing the power of formal technology and automating it to make it easy to use for mass designers, we learned a lot about how to extract the real intent of the designs for complete and accurate analysis, how to optimize the formal analysis engines for high performance, how to simplify the user interface and reporting for maximum productivity, and how to architecture the tool flow to enable sign-off.

Over the years we have accumulated lots of knowhow and applied these techniques to different applications. For example, Meridian CDC has been used in production flows at dozens of companies and has helped tape out thousands of complex designs in the last 8 years. The ultimate goal for our customers is to be able to sign-off on CDC verification. Therefore we have adapted our philosophy and approach to CDC verification based on some basic principles:

  1. We require more thorough environment setup because this provides the necessary confidence that CDC analysis will be accurate and complete so our users can sign-off on CDC verification in the end; The “setup-lite” approach taken by our competitors can leave holes in CDC verification and nasty surprises late in the cycle; 

  2. We identify the root cause of CDC issues and only report that rather than all the symptoms of it so that users don’t have to read through a huge report with lots of noise. It is impossible to sign-off when one can’t even go through and examine each line in the report;
  3. Our structural and formal analysis are based on actual design principles to manage metastability rather than design templates, therefore Meridian CDC can handle more diverse designs styles;
  4. We offer a layered approach to CDC verification at multiple levels, starting from ensuring correct environment setup, to precise structural analysis, to customized formal analysis, and to CDC verification using simulation. This layered approach ensures all holes are covered to achieve CDC sign-off.

Extending all the knowledge learned to simpler applications such as linting and constraints management is a much easier task. Other companies which started with simple technology like linting and now are trying to extend their solutions to formal are having a much deeper learning curve and are faced with a much harder task to conquer. We benefit from climbing the tallest mountain early. Now we can stand high, see farther and go farther. I think that’s our strength”.

Real Intent is poised for continued success in the years to come. We thank our customers and industry partners for the support along the way. We will keep focusing on providing the best products and excellent customer support to contribute to the growth of the semiconductor and EDA industries and our society at large.

Fairs to Remember

Tuesday, February 8th, 2011

Real Intent participated in two events in Japan the last couple of weeks – EDSFair 2011 and Tokyo University Symposium. The followings are some of the highlights of the two events.

EDSFair 2011

EDSFair is a moderate size trade show for EDA companies held in Yokohama near Tokyo. Like DATE and DAC, it is accompanied by a parallel technical conference. It is an opportunity to network with electronic design companies in Tokyo, Osaka, Kyoto and some other nearby high-tech centers.

The show was held on Jan 27 and 28 (Thurs and Friday). The attendance was reasonable. In fact, the show looked quite busy post-lunch on Friday.

Real Intent got great traction at the show by exhibiting its leading edge software: Lint, Automatic Formal Verification, X-Verification, Clock Domain Crossing (CDC) verification, and Timings Constraints Management and Verification. In particular, the presentations on X-Verification and CDC verification were well received with many serious follow-ups.  Many attendees from large semiconductor companies seeking better solutions in the front-end verification space were very impressed with Real Intent’s high performance and high capacity Lint and CDC solutions which offer 10X improvement over competition. We got a lot of well qualified leads and it was a great show to start the year for Real Intent.

The next EDSFair will be held in October 2012 in conjunction with a semiconductor industry tradeshow so this was the last one held in the cold Japan winter. But it was well worth remembering.

Notes from Katsuhiko Sakano, General Manager of Real Intent K.K. in Japan



Tokyo University Symposium

The next stop after EDSFair was the “Advanced Design Methodology for VLSI Symposium” at Tokyo University graciously organized by Professor Masahiro Fujita. It was our privilege to participate. Tokyo University is a leading university in Japan and Prof. Fujita is a distinguished researcher in electronic design. 

The symposium brought together in one forum Real Intent with NextOp and SpringSoft. In my opinion, these three companies are the thought leaders today in advancing verification technology for the next generation of chips. 

NextOp presented its novel technology that finally makes available the automatic generation of assertions and functional coverage. SpringSoft presented new technologies for fast debug and verification closure. One of the ideas they presented had to do with mining the simulation output database in interesting ways for faster debug.

Real Intent gave the audience an  intuition and solutions for two verification problems that have become critical bottlenecks in the design flow: (1) the problem of X’s in simulation, and (2) the problem of verifying the humongous number of asynchronous interfaces on today’s chips. 

The program was led by a keynote by Maxeler Technologies on industrial-strength high-performance computing with an FPGA-based platform developed by the company.

All in all, the symposium was a very satisfying technical program that covered the state-of-art in high-end design, specification, implementation verification and debug. 

The audience consisted of faculty, students and electronic design professionals from local companies. Some of the companies in the audience were large design houses like Hitachi, Toshiba and Fujitsu as well as a number of smaller companies providing verification services, engineering recruitment and sales distribution. It was an excellent opportunity to network with the local professionals in terms of understanding their verification needs and projecting Real Intent as a key provider of enabling technologies for the verification of next-generation chips. 

The symposium finished on a high note with a drawing for an iPad. Appropriately, it was won by a student of Prof. Fujita’s.

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