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Lauro Rizzatti - General Manager, EVE-USA
Lauro Rizzatti - General Manager, EVE-USA
Lauro is general manager of EVE-USA. He has more than 30 years of experience in EDA and ATE, where he held responsibilities in top management, product marketing, technical marketing and engineering.

Hardware Emulation for Lowing Production Testing Costs

December 20th, 2010 by Lauro Rizzatti - General Manager, EVE-USA

The sooner you catch a fault, the cheaper it will be, or so the user surveys tell us.  These surveys, conducted by various data gathering services, are meant to determine the cost of pinpointing design faults during the creation of chips.  Each one proves conclusively that costs increase by a factor of 10 at each step in the development cycle. 

It’s hard to find a better example than the infamous Pentium bug dating back to 1994.  The cost to fix the bug that found its way inside thousands of PCs was more than a billion dollars because the design fault made its way into a manufactured product.  Talk about breaking the budget and tarnishing a stellar technical reputation!

Of course, EDA companies have long touted their design-for-testability (DFT) methodologies.  Thorough and exhaustive functional verification during the development cycle is still a good strategy and an economical way to find and remove design faults, though it’s becoming less practical.  Systems-on-chip (SoCs) are populated with arrays of cores, including CPUs and DSPs, embedded memories, IP peripheral blocks, custom logic and so on.  With all of this, functional verification becomes a major bottleneck before tapeout, reinforcing the industry-wide consensus that functional verification consumes in excess of 70 percent of the development cycle. 

And, that may not be enough!  When undertaking functional verification using HDL simulators, the trade-offs between the amount of testing and the allocated time for the task often leaves undetected faults inside the design.

Herein lays the conundrum.  Functional verification can detect faults early in the design cycle, reducing the cost of finding them.  And yet, a thorough job of cleaning a design would take such a long time, the cost would be over any reasonable budget.

A new generation of hardware emulators is changing all of this.  Unlike traditional emulators that cost small fortunes, limiting ownership and adoption to a few units at large companies with equally large budgets, these new functional verification systems are much more cost effective.  They’re also faster. 

These emulators, implemented on small footprints, are powered by the latest FPGAs and driven by robust software.  They are accessible to SoC engineers and embedded software developers and can be used throughout the design cycle.  Designs target a variety of fast-paced markets, including networking, communications, multi-media, graphics, computer and consumer.

An example is ZeBu from EVE.  It supports a comprehensive test environment to exhaustively exercise all functions of a design.  Its interactive debugging –– a prerogative of the software simulator –– enables a higher degree of verification/testing than possible with traditional software tools.

Design teams have finally found a means to uncover those nasty and difficult bugs, saving the budget and making management happy.  These new functional verification tools, such as emulation, offer orders of magnitude more testing than available using software tools but with the same financial investment.  Check the recent user surveys and see for yourself.

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