Lauro Rizzatti - General Manager, EVE-USA
Lauro is general manager of EVE-USA. He has more than 30 years of experience in EDA and ATE, where he held responsibilities in top management, product marketing, technical marketing and engineering.
Hardware-Assisted Verification Tackles Verification Bottleneck
October 4th, 2010 by Lauro Rizzatti - General Manager, EVE-USA
An often-repeated industry mantra is that verification takes up about 70 percent of the development cycle, making it the most time-consuming piece of chip design today. Every indication that we’ve seen over the past 10 years confirms this number. And while a host of software-based verification tools have been deployed to tackle the verification bottleneck, design teams are turning to hardware-assisted verification platforms to accelerate hardware debugging and software test and integration. As a result, they’re often successful at reducing their verification budget and beating time-to-market pressures.
Let’s examine this move toward hardware-assisted verification.
Software development can’t wait for working silicon, which means that design teams need to a fail-safe way to verify that their chips will work as intend as they run embedded software. All the while, they’re grappling with shortened development cycles and designs that reach billions of application specific integrated circuit (ASIC) gates and millions of lines of code.
This means that a design team needs to create a working prototype for software development as early as possible and before the end of the hardware design cycle. The prototype must fit into the general hardware design flow or the design team risks extending the design cycle.
More and more, hardware-assisted verification platforms are used to simultaneously validate hardware and software and, generally, fall into either emulation or field programmable gate array (FPGA) prototyping categories.
Emulation has had a reputation for offering large capacity and good hardware debug capabilities, but is reputed to be slow, expensive and poorly suited for validating embedded software. Conversely, FPGA prototypes are cheaper and faster, but do not have hardware debug capabilities and take longer to build and test.
Many design teams with a large budgets use both approaches.
That’s changing with the latest generation of hardware-assisted verification platforms able to offer features and benefits of both. Suppliers of these platforms have combined speed for embedded software validation with hardware visibility and debug, giving design teams a way to verify hardware and software as a fully operational embedded system.
One popular emulator based on an FPGA architecture is used for simultaneous hardware and embedded software verification. It has the speed to validate embedded software and the ability to provide full internal signal visibility for effective hardware debug.
In general, ASIC prototypes require manual code changes for FPGA implementation, followed by logic synthesis and manual partitioning across multiple FPGAs, then place and route. Designers repeat these steps each time the design is changed, making the prototype ineffective for hardware verification. This latest generation emulator automatically completes these steps without modifying the original system-on-chip (SoC) source code. It handles complex clock processing, memory generation, multiplier/ALU logic, bus resolution and multiple-data-rate (XDR) wrapper generation.
Further, it can compile incremental changes to either the testbench or design under test (DUT). And, it uses the same hardware and models across the design cycle, making it a single platform for hardware and software verification.
Hardware-based verification platforms are giving design teams a way to break the verification bottleneck and reduce the verification budget. They’re finding that they can now use a single platform to handle hardware/software architectural tradeoff analysis, hardware debug, hardware regression, software integration and embedded software validation. Now, that’s a mantra worth repeating.