I still remember the enthusiastic talk around the 10-year EDA retooling cycle in 2000. There was optimism fueled by the dot-com boom. Moore’s Law was in full force. Communications industry was in infancy, ready for innovative new products. Products were evolving quickly, pressuring designers to produce more and more in less time. This, in turn, was fueling an unprecedented demand for new and innovative EDA solutions.
Those were the days… EDA startups were abundant. There were many trade shows, most notably DAC. Hotels were sold out! The big 3 had huge parties, and oh yes, design engineers could learn of all the new developments over the week. You really needed a good pair of walking shoes in those days… It was like going to a candy store!
From a methodology perspective, automation and re-use quickly became a big focus. Mixed signal designs, multiple clock domains and advanced power management schemes became the norm. Simulators did not have enough horsepower to test all aspects of a chip. Accelerators and emulators became more heavily used, but with them came additional issues.
Standards have evolved around key issues. The Verilog language evolved into SystemVerilog. Standards define good coding practices including re-use practices. LINT tools became more heavily utilized to improve the quality of the design and to ensure that re-use guidelines were followed.
It is now 2010. The big EDA companies have adopted an all inclusive volume sales model, putting the squeeze on the smaller companies that have to compete with their “free” software. As a result, there are fewer EDA companies providing innovation. DAC is a much smaller show. And we don’t hear much about this 10 year re-tooling cycle.
But Moore’s law is still active, albeit at a slower pace. Chip sizes continue to grow and complexity continues to increase. The time to market pressures are as strong as before, if not worse. Verification continues to have key challenges that beg for automation. And, not surprisingly, the 10-years old software has slowly aged and is no longer meeting today’s design requirements.
Some lint tools run for 10s of hours on designs when it is possible to run in minutes. Some CDC tools run for days when it is possible to run in hours. Some rule checking tools produce 100s of thousands of warnings – the wasted debugging effort may add up to an army of engineers. The confluence of clocking domains, power domains and DFT requirements have added significant pressure on design methodologies.
There may be fewer EDA companies these days but innovation is still going strong. Products for the next 10-years are available and getting adopted. Precise Lint tools with blazing performance are available. Precise CDC tools make it possible to achieve reliable sign-off on today’s designs. New innovations are underway for solving complex issues such as X-Optimism and X-Pessimism in simulation. Automatic Formal Analysis tools quickly improve design quality with minimal effort. SDC tools ensure the effectiveness of time consuming STA efforts. The 10-year retooling cycle is in effect again.
So what tools are in your flow? Are they current? Are they working well? Can your supplier respond to your needs? Are you getting what you paid for?
You need today’s innovations to deal with tomorrow’s problems!