Lauro Rizzatti - General Manager, EVE-USA
Lauro is general manager of EVE-USA. He has more than 30 years of experience in EDA and ATE, where he held responsibilities in top management, product marketing, technical marketing and engineering.
Celebrating Freedom from Verification
July 5th, 2010 by Lauro Rizzatti - General Manager, EVE-USA
Happy Fourth of July! If you’re celebrating Independence Day today, chances are you have the time to do so because of a set of tools that freed you from the drudgery of endless verification cycles.
Yes, let’s give thanks as an industry to the plethora of commercial tools that reduce the amount of time consumed by laborious verification tasks. They take many forms today, from hardware emulation and formal verification to simulation and acceleration, to name just a few. All have been developed to reduce the verification portion of the design cycle –– purported to be in the range of 70% –– and to lessen the burden you carry.
Each year, the verification challenge gets worse as SoC design sizes and complexity increase, stressing and periodically breaking existing design flows. New data shows that the average design size is now exceeding 10-million ASIC-equivalent gates –– don’t get me started on what’s an ASIC-equivalent gate, I’ll save that for another post –– with individual blocks running between two- and six-million ASIC-equivalent gates.
Exercising each and every one of those gates by an old rule of thumb would require a number of cycles equivalent to the square number of gates. That is close to a quadrillion cycles –– yes, that’s a one followed by fifteen zeros. That’s a lot of verification cycles and a lot of headaches.
And, lest we forget, the time-to-market push continues unabated.
How do we cope with this triple challenge of gates, cycles and time to market and tame the tiger? Only functional verification can thoroughly debug a design before silicon availability, if you have the time to do it.
Maybe not all is lost. Exhaustive functional verification carried out via a RTL simulator is no longer a practical or viable alternative because of its abysmal performance –– they are just too slow to fully analyze and verify larger chips. And, almost all of today’s chips are large and getting larger.
Emulation serves as a neat solution to the runtime problems that afflict these 25-year old logic simulators. They are used to identify bugs and can alleviate the functional verification bottleneck by executing at megahertz speeds. They accelerate the time needed to develop and validate hardware or embedded software design within the constantly shrinking schedule. Emulators improve the product quality by increasing the level of testing of a design to meet the quality standards expected in today’s feature-rich electronics devices.
You can forget whatever you may have heard about the older “big box” emulators. New generations of modern hardware emulators fit in small footprint chasses and deliver execution speeds close to real time, making them useful as in‑circuit test vehicles. While their runtime performance is impressive, they are far less expensive, easier to use and flexible enough for the current SoC project or the next one.
Even with these tools, verification continues to be a time-consuming process and often the bottleneck, but many of them have given you the freedom to enjoy the day off. Celebrate the holiday and let freedom ring!