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Archive for June 18th, 2010

Verifying Today’s Large Chips

Friday, June 18th, 2010

Today’s chips are pushing the verification envelope with their size, integrated system-level functionality, and the nano-scale-driven bubbling up of previously second-order considerations. Also, diminishing returns from geometry-shrinks force designers into ever more aggressive control optimizations for timing and power, and manufacture-test considerations require fancier DFT structures on chip. The visible manifestation of these effects has been an increase in the variety of failure modes.

For example, new designs contain multiple clocks necessitated by a combination of clock-skew considerations and the diverse clocking requirements of SOC components. Consequently, failures from improper domain crossings are more common today. Similarly, low-power design techniques like clock and Vdd gating are now used more widely, creating new failure modes. Each new failure mode requires an additional verification step.

A key consideration in the design of verification tools and flows in the face of this challenge is that the many new verification steps are sequential and intertwined. It is the number of these iterative steps to the final working chip that kills productivity. In one pass of the verification flow, one must debug the clock domain interactions and timing constraints before full-chip functionality is verified, which, in turn, must be debugged before power management and DFT structures are verified. Any design fix for some failure mode requires that the entire pass be repeated – for example changes to functionality or a design resynthesis can perturb clock-domain crossings or timing constraints.

The more you postpone verification, the longer each step will be because it must analyze more of the design and, crucially, the manual debug process is less local to the failure location. Verification complexity grows exponentially with design size and the number of verification steps is greater for modern chips. Consequently, verifying later in the design cycle causes a substantial increase in the time to a working chip. Late-stage verification also forces more of the design to be reanalyzed post bug-fix than is truly necessary.

An intuitive solution is to verify early and to distribute the verification across design modules. With this, we achieve the dual goal of reducing the latency of each verification step and reduce the impact of sequentiality. By the time the design enters the later stages, the bugs that could have been found earlier should have been fixed and verification must focus on truly full-chip failures. Consequently, each late-stage verification step will be shorter; the number of bugs found will be fewer; and fewer passes of the multi-step verification flow will be required.

Since early verification is the purview of designers, such tools must follow three important guidelines:

-          Maximize automation

-          Apply simulation and formal methods surgically for specific failure modes so that the analysis time is commensurate with the emphasis on design rather than verification

-          Always return actionable information to identify and diagnose failures and better understand the design

Real Intent products enable early verification for key failure modes. Its Ascent family finds bugs in control-dominated logic without the need for assertions or testbenches. It performs sequential formal analysis to identify deep bugs requiring many clock cycles to manifest as symptoms. MeridianCDC finds bugs in clock and domain crossing implementations. MeridianDFT does testability analysis and finds bugs in the implementation of DFT structures. Finally, PureTime finds bugs related to improper timing constraints. The adoption of these early verification tools is essential today for designing working chips in an acceptable amount of time.


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