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Archive for June 7th, 2010

Will 70 Remain the Verification Number?

Monday, June 7th, 2010

It’s that time of year again.  The design automation community is about to descend on Anaheim for the yearly conference.  The build up of anticipation, the buzz and the extra effort preparing for our booth have me pondering the topic of verification.

With verification consuming 70% of the design cycle, will 70% of the exhibitors at DAC this year offer tools to solve the verification challenge?  We will see.  While the percentage may not reach 70, I am confident that many companies will offer a variety of new, old or repackaged techniques, methodologies and tools for a verification engineer’s consumption.

With an abundance of options and choices, could the verification tool categories make up 70% of the EDA tools category?  Well, that is our space, hardware emulation, and Real Intent’s in the formal verification area.  Add acceleration, assertions, debug, prototyping, simulation, testbench generation, TLM models, validation, functional qualification, static verification and the list is growing, but not quite overtaking the rest of the field.

Next are the attendees at this hallowed event.  One can’t help but wonder if 70% of attendees are verification engineers, given the mammoth effort to verify that a chip will work as intended.  Will 70% come from the U.S. or will we see some attendees from Europe, Asia and the rest of the world, as well?  What’s more, of this group, are they spending 70% of their time on the exhibit floor researching verification solutions and new technologies?  Or, for that matter, 70% of their CAD budget on verification tools?

And, lest we forget, does verification account for 70% of the yearly EDA revenue?  Not according to the EDA Consortium.  In 2009, Computer Aided Engineering (CAE) contributions to the EDA worldwide revenues were in the ballpark of 40%, which includes IC Physical Design and Verification, PCB and MCM, Semiconductor IP Products and Tools, and Services.  Within CAE, by adding all forms of verification, such as logic, formal, timing, analog and ESL, that number exceeds 70%.

Even if you’re not a verification engineer, verification must matter as SoC design sizes and complexity continue to outwit even the most sophisticated EDA design flow.  After all, the average design size is about 10-million ASIC gates, with individual blocks running between two- and four-million ASIC gates.  And, the push to get products to market is only increasing.

As DAC kicks off next week in Anaheim, the question is whether a company on the exhibit floor will have the breakthrough verification tool to crack the 70% barrier.  Many will have software and hardware that will help to reduce the insidious verification challenges.  Emulation, for instance, is emerging as a tool for debugging hardware and for testing the integration of hardware and software within SoCs ahead of first silicon.  Stop by EVE’s booth (#510) during DAC to see a range of hardware/software co-verification solutions, including super fast emulation.  You’ll walk away with greater understanding of ways to reduce the time consumed doing verification, a handy reusable tote bag, and chances to win one of two iPADs or one $100 visa check card. Stop by Real Intent booth 722 to see how Real Intent’s solutions bridge the verification gap in Lint, CDC, SDC, DFT and X-Prop verification. They are giving away some real good looking and useful carabiner flashlights and carabiner watches.

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