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Archive for June, 2010

My DAC Journey: Past, Present and Future

Monday, June 28th, 2010


I have a unique perspective on DAC since I have attended DAC in many different capacities over the last 15 years: as a poor student, a lucky customer, an excited vendor participant, an independent consultant, a free spirit and a hard working vendor organizer.  The following log describes the many DACs that I have attended and my impressions.

·1995 (San Francisco):  My first DAC as a graduate student. Our research group (Zhi Wang and me, led by Prof. Malgorzata-Chrzanowska Jeske) from Portland State University won the Design Automation Conference Scholarship Awards for our project “Fine-Grain Locally-Connected FPGAs; Synthesis and Architecture”. It was an exciting event for me since I had been in the U.S. for only one year. Being able to participate in the academic sessions and meeting with other researchers were simply fantastic!


·1996 (Las Vegas): As a CAD engineer from Lattice Semiconductor Corporation.  As a customer of EDA tools, I was treated to my very first expensive Sushi dinner by sales people of a vendor. The tradeshow floor was exciting and overwhelming. All the exhibitors, presentations, giveaways, magician shows stimulated all my senses. My colleague won a nice telescope in a drawing. Wow, it was amazing!


·1998 (San Francisco), 1999 (New Orleans), 2000(LA): As a core competency applications engineer from Cadence Design Systems. Those were good years at Cadence when the parties were lots of fun. I worked mainly in the suite to launch Cadence’s new equivalence checker. We were busy but I heard the floor traffic was down.


·2001 (Las Vegas): As a lead applications engineer from Real Intent. It was a very memorable DAC for me because Real Intent was a young startup at that time. We got a lot of attention from all kinds of people trying to learn about our “Intent Driven Verification” technology.


·2003 (Anaheim): As a free spirit.  I took time off after having my first daughter Makana. Without any obligations, I had a great time seeing old friends and keeping up with new development in the industry.


·2006 (San Francisco): As a new PhD graduate. I presented my research paper “Symmetry detection for large Boolean functions using simulation, satisfiability and circuit representation”, co-authored with Alan Mishchenko, Prof. Bob Brayton and Prof. Jeske. I also presented at the PhD forum on my thesis “Computing functional properties and network flexibilities for logic synthesis and verification”. I spent most of my time in academic sessions noticing the change of hot topics between years.


·2007 (San Diego): As an independent consultant. I was there to scout the market and see what’s new.


·2008 (Anaheim), 2009 (San Francisco): As a technical marketing manager for Real Intent. The product that I am responsible for, Meridian CDC, Real Intent’s flagship asynchronous clock domain crossing verification tool, got great attraction at these events. I remember talking nonstop for hours showcasing Meridian CDC’s advanced capabilities.



This year at Anaheim, I attended DAC as the director of technical marketing for Real Intent. This is the first time that I have been involved in orchestrating all the behind-the-scene work a vendor has to do to participate at DAC. I am struck by:

1.      How expensive it is to participate for DAC. Besides the huge cost of having a space at DAC, the cost of designing and building the booth, the cost of transporting the booth to and from the convention center, the cost of installing and dismantling the booth, and the cost related to staff travel add up very quickly. Some of the costs are so outrageous that I am surprised we all put up with these every year: $90 per hour for floor union labor from 8am to 4:30pm and $150 per hour overtime?  $270 to vacuum a 900 SF area? $50 for a gallon of coffee with $25 delivery charge? Why do the smart people in EDA pay so much money for so little service?


2.      The amount of time and effort needed to organize all activities. A successful tradeshow is a concerted effort  involving many groups of people: R&D to develop the new big thing to showcase at DAC, Sales to line up customer meetings, Marketing to create a theme and associated art work, update product literature, create product presentation and demonstration, Media to tell the public what will happen, Booth design firm to design a booth with a prominent presence while saving cost, Promotional company to select giveaways and DAC attire, Logistics firm for transportation to and from the convention center and within the convention center, Union labor for booth installation & dismantling (their lack of efficiency drove us nuts), Hotel for staff, and many more. After doing all these, I now have great appreciation of people who organize trade shows. There are a million details, tons of work.

The hard work paid off. Real Intent had a good show. We had many qualified people coming through our booth checking out our technologies. People all liked our stylish booth design with wavy frosty panels and 3 different shirt colors (red, green and purple).  We often got asked about the different shirt colors as people walked in our booth, and we proudly pointed to the colors of our 3 product families: Ascent, Meridian and PureTime.



DAC released preliminary attendance number for this year: full conference 1554, exhibit attendees 3444, exhibitors and guests 2557. The total number of participants 7555 is on par with last year’s total of 7996 [1]. However throughout the years, most people would say that the number of companies exhibiting and the attendance have gone down from the good days. The following are some of the factors that have contributed to this trend:

·With the high cost and huge amount of work involved, smaller companies may reduce presence or pull out;

·With the other smaller regional tradeshows, e.g. DVCon and SNUG, potential customers have less of a need to travel to DAC to meet all the vendors;  

·With the advancement of internet, all companies have extensive web presence so information can be accessible at the finger tips of potential customers. The need for people to gather information from the traditional tradeshows is somewhat reduced;

·The economy has definitely played a role in the trend we are seeing with DAC.


These make me ponder what value DAC brings and where the future lies. What are the goals for exhibitors and customers at DAC going forward?  And should DAC consider going virtual like FPGA Summit?

My answers coming from all the prospective that I had over the years are:

·DAC is a very unique event in that it is for both academic researchers and end users. It bridges the gap between academic researches and EDA tools. No other venue can conveniently bring the two together as DAC does.

·Though overall attendance has reduced, the key decision makers who attended the shows have not changed. The quality of conversation has definitely improved.

·Despite the cost and effort involved, DAC offers a window for potential customers to gauge the financial health of a company and get to know all the hard working technologists behind the scene. It is also a great opportunity for R&D to hear customer’s problems and issues first hand. This level of interaction and communication can’t be achieved elsewhere.

·As Real Intent grows geographically, every year I meet new people for the first time whom I have worked with over skype and email. It is exciting to get to know my coworkers a bit more personally.

·Besides, DAC is an opportunity to connect with old acquaintance. After all, our industry is a very small world.


If I could offer any suggestions for the future, I would recommend DAC to adopt SNUG’s approach with its recent designer community expo (DCE). All the booths are designed and setup for the vendors. All we had to do was to provide booth graphics. I know this removes the unique look & feel for vendors, but it was such an easy event for us to attend and the results were awesome. After all, it is the people and technology users care about mostly.


I certainly believe DAC will stay for many years to come, I will see you in San Diego!


[1] 47th DAC Announces Preliminary Attendance Numbers

Based on the math from years past, the definition of total attendees include conference attendance and exhibit attendance. Last year the total was 5299. This year it should be 4998 (1554+3444), a merely 6% drop. The total number of 6001 given in the press release included exhibitors, not full conference attendees. If we compare the total participants, which include all three categories, then last year it was 7996, again only slightly more than this year’s 7555. Am I missing something?


Verifying Today’s Large Chips

Friday, June 18th, 2010

Today’s chips are pushing the verification envelope with their size, integrated system-level functionality, and the nano-scale-driven bubbling up of previously second-order considerations. Also, diminishing returns from geometry-shrinks force designers into ever more aggressive control optimizations for timing and power, and manufacture-test considerations require fancier DFT structures on chip. The visible manifestation of these effects has been an increase in the variety of failure modes.

For example, new designs contain multiple clocks necessitated by a combination of clock-skew considerations and the diverse clocking requirements of SOC components. Consequently, failures from improper domain crossings are more common today. Similarly, low-power design techniques like clock and Vdd gating are now used more widely, creating new failure modes. Each new failure mode requires an additional verification step.

A key consideration in the design of verification tools and flows in the face of this challenge is that the many new verification steps are sequential and intertwined. It is the number of these iterative steps to the final working chip that kills productivity. In one pass of the verification flow, one must debug the clock domain interactions and timing constraints before full-chip functionality is verified, which, in turn, must be debugged before power management and DFT structures are verified. Any design fix for some failure mode requires that the entire pass be repeated – for example changes to functionality or a design resynthesis can perturb clock-domain crossings or timing constraints.

The more you postpone verification, the longer each step will be because it must analyze more of the design and, crucially, the manual debug process is less local to the failure location. Verification complexity grows exponentially with design size and the number of verification steps is greater for modern chips. Consequently, verifying later in the design cycle causes a substantial increase in the time to a working chip. Late-stage verification also forces more of the design to be reanalyzed post bug-fix than is truly necessary.

An intuitive solution is to verify early and to distribute the verification across design modules. With this, we achieve the dual goal of reducing the latency of each verification step and reduce the impact of sequentiality. By the time the design enters the later stages, the bugs that could have been found earlier should have been fixed and verification must focus on truly full-chip failures. Consequently, each late-stage verification step will be shorter; the number of bugs found will be fewer; and fewer passes of the multi-step verification flow will be required.

Since early verification is the purview of designers, such tools must follow three important guidelines:

-          Maximize automation

-          Apply simulation and formal methods surgically for specific failure modes so that the analysis time is commensurate with the emphasis on design rather than verification

-          Always return actionable information to identify and diagnose failures and better understand the design

Real Intent products enable early verification for key failure modes. Its Ascent family finds bugs in control-dominated logic without the need for assertions or testbenches. It performs sequential formal analysis to identify deep bugs requiring many clock cycles to manifest as symptoms. MeridianCDC finds bugs in clock and domain crossing implementations. MeridianDFT does testability analysis and finds bugs in the implementation of DFT structures. Finally, PureTime finds bugs related to improper timing constraints. The adoption of these early verification tools is essential today for designing working chips in an acceptable amount of time.


You Got Questions, We Got Answers

Monday, June 14th, 2010

Have you ever worried about:

  • Missing real bugs in a 10,000-line verification report?
  • Whether your design will function as intended?
  • Why there are RTL and netlist simulation mismatches?
  • When you can sign-off on clock domain crossing verification?
  • Whether your RTL has enough test coverage?
  • If you design constraints are correct?

DAC is an excellent time to connect with EDA vendors to get our concerns and questions answered!

Our team at Real Intent has worked very hard to create a comfortable space at DAC (booth 722) where you can come and meet with true technologists and attend Expert Corner Lectures to learn about the latest technology innovation in X-prop and CDC verification.

Real Intent’s automatic formal verification solutions are known for its solid analysis engines, superior performance and low noise report.  Seeing is believing, come and check out our product demos showcasing our latest technologies at DAC. You will also walk away with some real cool gadgets!

See you at DAC!

Expert Corner Lectures
Monday June 14 & Tuesday June 15, 2010, 4pm – 5pm
Real Intent booth # 722
Topic: “Efficient and Practical Prevention of X-Related Bugs

Abstract: It is painful and time consuming to identify X sources and chase their propagation between RTL and Gate representations. Such “X-Prop” issues often lead to a dangerous masking of real bugs. No clear solution has existed thus far to address this problem effectively. This lecture explains the common sources of X’s and shows how they can cause functional bugs. It then discusses the challenges that Real Intent has overcome in developing an efficient solution to assist designers in catching bugs caused by X propagation and ensuring X-robust designs.

Monday June 14 & Tuesday June 15, 2010, 5pm – 6pm
Real Intent booth # 722
Topic: “Achieve 100% CDC Signoff with Advanced CDC Verification

Abstract: Today’s SOCs have a multitude of components working with different clock-domains running at varying speeds. You have done CDC verification on your blocks, but how will you know you are done? This lecture highlights the advanced technologies that Real Intent has developed to help achieve 100% CDC Sign-off.

To register for both lectures, please visit

Will 70 Remain the Verification Number?

Monday, June 7th, 2010

It’s that time of year again.  The design automation community is about to descend on Anaheim for the yearly conference.  The build up of anticipation, the buzz and the extra effort preparing for our booth have me pondering the topic of verification.

With verification consuming 70% of the design cycle, will 70% of the exhibitors at DAC this year offer tools to solve the verification challenge?  We will see.  While the percentage may not reach 70, I am confident that many companies will offer a variety of new, old or repackaged techniques, methodologies and tools for a verification engineer’s consumption.

With an abundance of options and choices, could the verification tool categories make up 70% of the EDA tools category?  Well, that is our space, hardware emulation, and Real Intent’s in the formal verification area.  Add acceleration, assertions, debug, prototyping, simulation, testbench generation, TLM models, validation, functional qualification, static verification and the list is growing, but not quite overtaking the rest of the field.

Next are the attendees at this hallowed event.  One can’t help but wonder if 70% of attendees are verification engineers, given the mammoth effort to verify that a chip will work as intended.  Will 70% come from the U.S. or will we see some attendees from Europe, Asia and the rest of the world, as well?  What’s more, of this group, are they spending 70% of their time on the exhibit floor researching verification solutions and new technologies?  Or, for that matter, 70% of their CAD budget on verification tools?

And, lest we forget, does verification account for 70% of the yearly EDA revenue?  Not according to the EDA Consortium.  In 2009, Computer Aided Engineering (CAE) contributions to the EDA worldwide revenues were in the ballpark of 40%, which includes IC Physical Design and Verification, PCB and MCM, Semiconductor IP Products and Tools, and Services.  Within CAE, by adding all forms of verification, such as logic, formal, timing, analog and ESL, that number exceeds 70%.

Even if you’re not a verification engineer, verification must matter as SoC design sizes and complexity continue to outwit even the most sophisticated EDA design flow.  After all, the average design size is about 10-million ASIC gates, with individual blocks running between two- and four-million ASIC gates.  And, the push to get products to market is only increasing.

As DAC kicks off next week in Anaheim, the question is whether a company on the exhibit floor will have the breakthrough verification tool to crack the 70% barrier.  Many will have software and hardware that will help to reduce the insidious verification challenges.  Emulation, for instance, is emerging as a tool for debugging hardware and for testing the integration of hardware and software within SoCs ahead of first silicon.  Stop by EVE’s booth (#510) during DAC to see a range of hardware/software co-verification solutions, including super fast emulation.  You’ll walk away with greater understanding of ways to reduce the time consumed doing verification, a handy reusable tote bag, and chances to win one of two iPADs or one $100 visa check card. Stop by Real Intent booth 722 to see how Real Intent’s solutions bridge the verification gap in Lint, CDC, SDC, DFT and X-Prop verification. They are giving away some real good looking and useful carabiner flashlights and carabiner watches.

S2C: FPGA Base prototyping- Download white paper

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