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Dr. Pranav Ashar, CTO
Dr. Pranav Ashar, CTO
Dr. Ashar brings two decades of EDA expertise to Real Intent. He previously worked at NEC Labs (Princeton, NJ) developing formal verification technologies for VLSI design. He authored about 70 papers and co-authored a book titled "Sequential Logic Synthesis." He has 35 patents granted and pending, … More »

We Sell Canaries

May 10th, 2010 by Dr. Pranav Ashar, CTO

When someone asked me the other day what Real Intent does, I told him, only half in jest, that we make and sell canaries. If you think about it, the verification tools we develop are the proverbial canaries for the chip-design coal mine. Their role is for them to be used in the advance party to give early warnings of bugs lurking in the chip. Used in this manner, our tools prevent late-stage blow-ups in chip functionality that can potentially ruin profit margins and may be even subvert an entire business model.


Talking about business models makes me think of start-up companies. It is very hard today to get a start-up company venture funded if it has a significant chip design component in its development roadmap. This bias is not wholly without reason. Hardware design is expensive and having to design your own chips makes it more so. While getting the product wrong the first time around is expensive for any start-up, it is especially so for a hardware company. If you need to reposition your hardware product or fix problems in it, it is all the more difficult and expensive if it involves redesigning a complex homegrown chip. The realization of the company’s product concept, and indeed the entire business model, becomes a prisoner of the chip design latency. You must get the chip right-enough quickly-enough to leave any wiggle room in the business model.


The risk is scary, but so is mining coal. Coal continues to be mined despite its risks and so must entrepreneurial initiative in chip design be perpetuated. As in coal mining, systematic processes must be instituted in chip design to mitigate risk. Accidents cannot be done away with, but can certainly be reduced in frequency.


One of the important technologies with the potential to significantly mitigate chip design risk is the application of pre-simulation static verification tools that target chip design errors in the context of specific failure mode classes. The technology has matured enough in the last decade to provide tangible value today. If I was evaluating a chip-design-heavy business proposal at a venture capital firm, I would certainly gate the funding based on whether the founders have experience with and instituted the use of static verification tools as an integral part of their chip design process and roadmap.


Real Intent has been a pioneer in this space and provides pre-simulation static verification tools that address some of the key failure modes. Real Intent’s Ascent product family finds bugs in control-dominated logic without the need to write assertions or testbenches. Because Ascent tools perform sequential formal analysis, they can even identify deep bugs that take many clock cycles to manifest as observable symptoms. Our Meridian tool family finds bugs in the implementation of clocks and clock-domain crossings. These bugs result from a confluence of timing and functionality and can be so subtle as to require a specific combination of process parameters for them to materialize. If ever there was a canary for chip design, it is Meridian. Finally, our PureTime tool family finds bugs to do with incorrect timing constraint specifications. Like clock-domain crossing bugs, these bugs too arise from a confluence of timing and functionality. Real Intent continues to develop new tools of this ilk to target additional failure modes. Our goal is to help make chip design risk acceptable again.


The adoption of these tools is up to you. Do you have a canary in your design flow?

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