Yoav co-founded and managed Satris Israel, a services company which later transferred all of its activity to Satris Group. Prior to that Yoav was an independent verification consultant providing services to numerous semiconductor companies building cutting edge environments as well as to … More »
Do you have the next generation verification flow?
April 19th, 2010 by Yoav Arnon
I have been involved in verification projects for the last ten years. One thing I can say for sure is the level of complexity is ever rising for both design and verification. With more and more ASICs being designed with applications using high computing power for mobile consoles in the consumer market, the time to market has become critical and there is zero tolerance of being late. At the same time, the increasing power sensitive devices add to the functional requirements. The verification effort grows exponentially rather than in a linear manner with respect to the added features. The reason is simple, when the feature list grows in 30%, true verification requires not only 30% more feature checking but also cross feature verification. The higher demands coupled with shorter schedules make verification a challenging task.
In addition, globalization brought about knowledge sharing as well as creating tough competitions around the world. The rule of the game has become to deliver as fast as possible. As a result, the verification professionals need to be constantly on the look for the right technologies to be deployed in their verification flow in order to keep up with the pace of change and get ahead of competition. Verification flow can become a competitive advantage for a firm.
Random based coverage driven verification (CDV) is becoming an industry standard, and I believe that trying to deliver bug free ASICs or FPGAs using direct testing is practically impossible. The problem with CDV is that it involves a huge amount of engineering effort to build all the verification environments. This effort is at least as complex as the design itself and in many times even more so. It also requires dedicated teams specializing in environment development. The consequence is that the debugging process has longer iterations. Every time there is a test failure, two engineers, responsible for two different systems (design and verification environment) have to find out what went wrong, and only then can the mistakes be corrected. Bug fixing turnaround time can reach days or even weeks.
This is why automatic formal verification becomes useful. Automatic formal gives the team a way to find many bugs in a much cheaper (found earlier and therefore easier to detect, debug and fix) manner. These tools can prove that the design is clean of many issues that can be difficult to find using simulation. These issues include dead code segments, logical equations that are implemented incorrectly, thus giving a constant value, state machine which are deadlocked, pair state machines that lock each other, and even incorrect clock domain crossing problems such as data stability problems and incorrect control & feedback implementation.
One might say that these tools have no understanding of the functional specification, but in many cases functional bugs are direct consequence of these kinds of issues in the design. Another might say that most of these bugs can be found by well designed verification environments. Possible, however the great thing about automatic formal verification tools is that they do not need any verification environment development, which saves tremendous amount of time and effort. The concept is similar to lint tools. All you need is a short run script and the design itself. Therefore, when the designer is done with coding, he can use these tools, get answers quickly, and debug on his own with a very short turnaround time. All this occurs right when the RTL design is being developed, and it is usually much easier to debug early than the ones found weeks or even months later in the project, when verifying at a larger scope.
On the whole, automatic formal usage on top of CDV can save between 10% – 15% of the verification effort and give greater confidence that the design is ready for the next steps in the flow. In a competitive environment that we live in, and with the amount of resources put into verification, this saving can make a big difference. Taking the time right now to ensure that you have the right tools in the right place in your verification flow can save you time and money which equates to revenue for your company.