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Archive for February, 2010

Fostering Innovation

Monday, February 22nd, 2010

The news dominating the EDA communications channels of late is Synopsys’ recent acquisition spree of several small, well-regarded emerging companies with innovative technology.  I’m not ready to debate whether these moves signal the demise of the virtual platform market segment.  Instead, my guest blog is on fostering innovation.

Synopsys corporate strategy confirms my theory and one held by others as well:  Small companies are much better able to manage and promote innovation than the larger, more established players.

Most often, it’s a startup or emerging company that develops groundbreaking new technology and that’s due to any number of reasons.  Startups and small companies can offer an entrepreneurial environment conducive for innovative and creative thinking, and frequently encourage their employees to experiment.  These firms have a luxury not afforded by the large, more established companies –– they are not restricted by a hierarchy and a structure that can stifle creativity. 

Small and emerging companies are better able to focus an R&D team on a technical challenge, enabling them to take a fresh, even radical, approach.  They can be more aggressive in identifying and responding to market trends and industry needs, especially if the market capitalization is not large enough for an established player to justify an investment.

Two great examples of the entrepreneurial spirit of emerging verification companies are EVE and Real Intent.  With more than 70% of the development cycle of a system-on-chip (SoC) design being consumed by verification, these two companies are leading the way with innovative products.

I’m quite proud of EVE, an innovative emerging company formed in 2000 that’s turned the emulation market inside out.  Our goal, that we believe to be within reach, is to become the leader in hardware-assisted verification and embedded software validation for any-sized design, regardless of complexity and topology in any industry segment.  Over the years, EVE has unveiled several generations of emulation tools based on standard FPGAs that offer design teams a high return on investment. 

And, Real Intent, the formal verification leader that pioneered intent driven verification, underscores entrepreneurism at its best.  No one believed that formal verification could be commercialized after one company’s failure in the 1990s.  Instead, Real Intent, with its automatic formal verification software, has continued to defy expectations since 1999.

Of course, large companies have positive characteristics as well, just not entrepreneurial or especially innovative.  They often have vast resources for marketing programs and their sales channels are much better developed and coordinated then a startup’s.  These same large companies carefully track the progress of a startup and can be counted on to acquire them, when the timing’s right.  This is all part of the EDA ecosystem that’s worked for many years.

Startup, emerging company, large established players.  In an ecosystem such as EDA, we need both large suppliers and innovative small companies to keep driving and encouraging technological advances.

CDC (Clock Domain Crossing) Analysis – Is this a misnomer?

Monday, February 15th, 2010

The high-tech industry is chock-full of acronyms. Each time a new problem is identified, out comes a new acronym that quickly gets standardized. It is very typical for complex new problems in, for example, our VLSI design industry to take years to understand and solve fully. Unfortunately, in many of these cases, the new acronym gets co-opted by a premature solution or a solution to a subset of the actual problem rather than be associated with the fundamental problem itself. The end result can be confusion and miscommunication as customers who use these incomplete solutions with the fancy acronyms do not realize that their problem is not fully solved and end up with project failure.


A revealing instance of this phenomenon is CDC – Clock Domain Crossing – analysis. As asynchronous crossings became more mainstream because of larger dies and greater system-level complexity on chip, it became clear that managing metastability was of paramount importance. The analysis of the design for proper metastability management came to be known as CDC analysis. Unfortunately, early solutions for CDC analysis only verified single-bit metastability management (synchronizers implemented as back-to-back flops) and data-bus metastability management (controlled by a synchronized common enable signal).  Designers’ understanding of CDC analysis even up to this day, as CDC analysis has become mission-critical for SOC designs, is that it only requires checking these two attributes.



In reality, the above two checks are just the tip of the CDC analysis iceberg. To begin with, they represent only a limited checking of metastability management. In addition, clock domain analysis must check for many more issues than just metastability management like the ones listed here:

-          Data correlation when you have fast to slow clock crossings

-          Cycle jitter tolerance in data crossings

-          Cycle jitter in control crossings

-          Glitch issues even when control busses are gray coded

-          Glitch issues with clock gating implementation

-          Re-convergence of signals synchronized separately to a single clock domain

-          Correct implementation of asynchronous FIFO protocols

-          Correct implementation of resets that cross multiple domains


As with metastability verification, all of the above issues are very difficult to characterize and verify with simulation-based techniques.  There have been many silicon re-spins as a result of not comprehensively verifying the above issues. Examples of failures we have seen happen in practice are quite revealing:

-          An asynchronous reset-control that crossed clock domains but was  not synchronously de-asserted, causing a glitch in control lines to an FSM

-          Improper FIFO-protocol controlling an asynchronous data crossing resulting in a read-before-write resulting in functional failure

-          Reconvergence of synchronized control signals to an FSM that were not gray-encoded, resulting in cycle jitter that, in turn, caused a transition to an incorrect state

-          Glitch in a logic cone on an asynchronous crossing path that was latched into the destination domain resulting in corrupt data being captured

-          Gating logic inserted by back-end tools for power management resulted in glitches on a clock


Verifying the above issues must use a combination of structural analysis and static formal property checking. Older tools that do only a limited amount of checking but continue to use the CDC moniker do the customer a disservice. They also do a disservice to modern tools like the Meridian product family from Real Intent that provides the most comprehensive analysis of CDC related issues.    Meridian does this by identifying all asynchronous crossings, verifying proper metastability management in crossings, comprehensively verifying that logic in asynchronous crossings is glitch free and by verifying asynchronous crossing control protocols.  Since logic is inserted by back-end tools into clock nets, it is important that the tool be able to run on a netlist. Meridian is the only CDC tool that can be run on netlists as well as on RTL, recognizing all asynchronous crossing controls including FIFO’s. Meridian is also the only tool that enables CDC checks to be performed in simulation in addition to static structural and formal analyses.


So, beware of acronyms! Make sure you know what they really represent.

EDSFair – A Successful Show to Start 2010

Monday, February 8th, 2010

From Prakash Narain, CEO of Real Intent

I have to admit that I was apprehensive going to EDSFair in Yokohama this year. Even though the economy is getting better, it is hard to know how many people will actually go to tradeshows. I was pleasantly surprised – EDSFair 2010 turned out to be a wonderful success for us.

Prior to the show, we announced that Professor Masahiro Fujita from University of Tokyo has joined Real Intent as a technical advisor, and that we have shipped Ascent Lint 1.2 with added new features.

The flow of visitors at EDSFair was steady throughout and kept us relatively busy for the two days. As we also noticed at DAC, visitors to the booth were very knowledgeable, patient and had done their homework.  They generally requested detailed demos of the Ascent, Meridian and PureTime product families, had excellent questions, and finished with follow up plans. Overall, it was a very productive two days allowing us to touch base with many of our key existing and potential customers.

I also had a press meeting and gave a seminar on cost effective application of formal technology to improve overall design verification flows. Both were well received.

The methodical work culture in Japan contributes in no small way to the success of EDSFair.  For example, new exhibitors at EDSFair are formally introduced to the audience by a Japanese expert.  This is followed by an organized tour where the audience is brought to the booth and the vendors are given an opportunity to highlight their products. Then there is a brief question and answer session.

We all had a good time at the show. The warmth of the people more than compensated for the cold weather outside!

With a successful EDSFair to start the year, now we are preparing for DVCon 2010 this month. We wish for the success of DVCon 2010 for all exhibitors and attendees.

From Katsuhiko Sakano, General Manager of Real Intent K.K.

リアルインテント社は2010年1月28日(木)と29日(金)の両日、EDSF(パシフィコ横浜)に Ascent(テストベンチ無しの自動リント検証), Meridian(CDC検証), PureTime(SDC及びタイミング検証)ファミリ製品のデモを交えて出展しました。予想以上に既存ユーザー方々や新規の方々も含め120名様以上と お会いすることができ、フォーマル検証及びデザインフローの見直しを検討している方の多さに驚いた。今後更に設計上の問題点を把握し、費用対効果が最も高 い弊社のフォーマル検証ツールを提案していきます。


昨年のリーマンショックの影響以降、US同様に日本も不景気が続いているのだろう。今回は特にリクルターの方の多く来場していてブース毎に人材募集 しているかどうか確認しているのが印象的だった。またEDSFは年に1度のビックイベントでもあり以前の会社の同僚や友人に会うことも同窓会気分でとても 良いところがあります。しかし来年は今年同様な形態で行わるかは大手3社の参加次第でしょう。


Ascent Is Much More Than a Bug Hunter

Monday, February 1st, 2010

Real Intent’s Ascent family of front-end RTL verification tools serves multiple functions in the verification flow.  The most important is that Ascent automatically finds functional bugs that are difficult to catch in simulation.   While finding bugs early on is very important in itself, Ascent is much more than a bug hunter.  Ascent also improves code coverage, saves simulation cycles, and reveals logic optimization potential. Some of these benefits are discussed here.

Code coverage is an important metric for simulation sign-off. Verification teams try to get as close to 100% coverage as possible. It is common for projects to struggle to achieve the 100% coverage due to a combination of reasons:

  1. A logic bug prevents a code block from being exercised
  2. A hole in the simulation test plan prevents a block of code from being exercised

The typical hard-to-detect unreachability bug is caused by unintended correlation between deeply nested control statements. This is very hard to detect in simulation since the test plan must exhaust all combinations of control values to determine that the nested block is unreachable. In other words, deeply nested unreachable blocks waste many simulation cycles, result in less than desired coverage, and, at the end of the simulation, one may still not be sure whether the block is truly unreachable.

Finding such unreachable blocks or demonstrating that hard-to-reach blocks are in fact reachable is relatively easy for Ascent’s formal engines. By using Ascent early on, the verification team can determine and fix unreachability issues before simulation is begun so that simulation cycles are not wasted trying to obtain unachievable coverage. On the flip side, Ascent can also help determine that a block not yet reached in simulation is in fact reachable, thereby indicating to the verification team that the test plan needs to be enhanced. Even better, Ascent can be used to find simulation traces to reach the difficult blocks.

Ascent also reveals optimization potential for simplifying designs.

For example, Ascent uses its deep-sequential formal engines to check for constant nets, constant expressions, unreachable states and unused state bits within a design. Because of the deep sequential analysis required to arrive at these results, the reported constant nets or expressions are often not easily identified manually. Those constants could be design bugs or opportunities for design simplification. A common reason for the presence of such constants is the interaction between new constraints and legacy RTL code, or the effect of system-level constraints on deeply embedded blocks.  An original fragment from a real design where Ascent detected a constant expression is shown in Figure 1(a).  Due to a programming requirement, the following constraint was imposed post facto on the inputs:

assume property @(posedge clk) disable iff (rst) (B==1’b0) |-> (A==1’b0) && (C==1’b0)

As a result, Ascent reported Y as a constant, meaning that the logic can be simply replaced by Figure 1(b).  This change, of course, also results in further simplification in downstream logic.

In summary, Ascent can play a key role in achieving very high coverage with a much smaller amount of simulation as well as find optimization potential in your design – it does much more than just find bugs.

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