Dr. Pranav Ashar, CTO
Dr. Ashar brings two decades of EDA expertise to Real Intent. He previously worked at NEC Labs (Princeton, NJ) developing formal verification technologies for VLSI design. He authored about 70 papers and co-authored a book titled "Sequential Logic Synthesis." He has 35 patents granted and pending, … More »
Verification Challenges Require Surgical Precision
January 11th, 2010 by Dr. Pranav Ashar, CTO
It has been interesting to note that, per the Q3 2009 EDAC market survey, design companies continued to buy functional verification tools even through the recent downturn. The prognosis is that verification spending will continue to rise. While this is good news for EDA companies, it is also an indicator of the industry’s inability to contain the verification problem as design complexity continues to rise in terms of the number of transistors and the system-level functionality on a chip.
Newer chips have additional failure modes that were not issues before. For example, approximately 85% of the designs today contain more than one clock domain. This is necessitated by a combination of clock-skew considerations as well as the diverse clocking requirements of system-level components on a chip. As a result, chip failures arising from improperly designed clock-domain crossings have become increasingly common. Similarly, low-power design techniques like clock gating and Vdd gating are also being used much more widely now, creating new failure modes that did not exist in previous chip generations.
Unfortunately for the design industry, there is no one-stop solution to the verification problem any more. While simulation has served the industry reasonably well thus far, its viability as the mainstay of the verification flow is being marginalized by the sheer complexity of checking for the newer failure modes. For example, using simulation to check clock domain crossings is not very effective given that these failures arise as a result of corner case confluences of timing and functionality.
We believe what is required is that more attention be focused on identifying important productivity sinks to provide effective solutions targeting these specific, isolated and self-contained verification problems. Usually, the design principles involved are well understood and hence the characteristics of the specific error modes can be clearly identified. Specialized and customized technologies that are based on synergetic integration of structural and formal techniques are the best solutions for detecting errors for these classes of issues. A well known success story of applying specialized technology to solve a narrow problem has been the wide and easy adoption of equivalency checking between RTL and Gate representations. Similarly, we believe that specialized technologies such as clock-domain crossing verification, low-power verification, X-behavior verification etc will also be widely embraced by the design community in the near term, making these tools an integral part of the design and verification flow.
The availability of these razor-sharp technologies targeting specific failure modes allows verification to be approached in a surgical manner with consequent improvements in design quality, productivity and return on investment. After all, even the best surgeon needs the right tools to be effective!