Hope you all had a wonderful holiday season filled with happy memories, good food, and presents from your wish list!  At Real Intent, we welcomed two beautiful babies into our extended family during the holidays: Ryan Ayden Eram and Ebba Anthony Patterson! What better presents to keep us all motivated to work hard to improve the lives for our children!

As a new year present to the industry and our loyal customers, Real Intent announced the release of Meridian CDC version 4.0 on January 11. This release incorporates numerous enhancements and speedups. We will be covering many of the features in more detail in later blogs, but here are a couple of highlights:

1. Real Intent’s Meridian CDC product has been the performance and capacity leader for some time now and the 4.0 release builds on the leadership with significant additional performance and capacity improvements (up to 5X) in structural analysis, design upload and GUI debug.  Meridian CDC 4.0 makes full chip CDC verification on 100+M gate SoC designs a reality and enables design managers to enforce full-chip CDC verification as a first-order sign-off requirement.
2. Meridian CDC 4.0 makes it much easier and faster to setup the design environment (clock, reset, mode select, stable value, input and output domains through SDC translation and automatic design analysis) so that the time to the first useful CDC analysis is minimized. Our continuous efforts in this regard are testament to our customer-centric perspective. We truly believe that in addition basing our products on strong technology foundations, we must also ensure that we do our utmost to make our products the most usable.

Our existing customers are already benefiting from the speedup and added functionality in 4.0. Meridian CDC is the flagship product at Real Intent, and we have a clear focus and devote significant resources to keep it so. The team is already onto the next release target with even more exciting features and improvements to come.

As noted by Prakash Narain, CEO of Real Intent, “Meridian CDC 4.0 release represents a milestone in the industry for delivering a CDC verification solution that can be used to achieve complete CDC sign-off for large and complex SoC designs from RTL to gate.”

The last decade has seen a sea change in integrated circuit design and verification. Around the year 2000, the Intel Pentium 4 had 42 Million transistors and was built on a 180 nm process, with CPU and interfaces built on different chips. A mere ten years later, Intel’s cloud server, Westmere EX, has 2.6 Billion transistors and was built on a 32nm process. It has 10 64-bit x86 CPUs, graphics, DDRs, virtualization, QPI, L3 Cache, a whole system on the same chip. It is mindboggling to think about the increase of complexity in IC design and verification in just a decade.

Electronic Design Automation (EDA) is a key enabler for the advance of IC/SoC designs. The advances in EDA tools parallel, as much as possible, the advances in IC design and verification. The development of Clock Domain Crossing (CDC) verification is a good example of this advancement.

In 2001, Cliff Cummings published a paper at SNUG called “Synthesis and Scripting Techniques for Designing Multi-asynchronous Clock Domains” ¹. In the paper, he talked about various asynchronous design techniques such as passing signals from fast to slow clock domains, passing multiple control signals, synchronizing datapaths by using handshakes and FIFOs. Cliff also proposed a CDC design methodology by adopting naming conventions and adhering to certain design partitioning principles.  In the paper, Cliff also discussed the impact of implementing asynchronous designs using synthesis and static timing analysis. Back then, Cliff was unaware of any CDC tools in the market. It was the era of simple CDC designs with less than 5 clock domains and manual review for CDC verification.

Things changed pretty quickly. In 2002, the first-generation CDC tools came to the market. Real Intent’s Verix CIV (Clock Intent Verification) was one of the pioneers in this field. The characteristic of the first generation tools was that they used structural analysis techniques to see if proper synchronization is in place and if there are unsafe CDC structures. While structural analysis alone was not sufficient to prove that all the asynchronous transfer protocols are safe, it was a step in the right direction and provided high value over manual review.

The second-generation CDC tools came around 2007, including Real Intent’s Meridian™ CDC.  These tools represented an advance in CDC verification technology by incorporating multiple verification techniques in addition to structural analysis. Formal analysis became an integral part of the solution in order to check for things such as data stability, pulse width, gray encoding and glitch potential. The tools also provided a simulation library and monitors so that users can perform CDC verification by injecting metastability effects during simulation and catching CDC violations using monitors. This advancement was necessitated by the number of bugs that slipped through to silicon due to clocking issues. According to Collett International and Farwest Research Group’s surveys conducted in 2002, 2004 and 2007, about 20% of chip re-spins were caused by clocking issues. As a result, functional CDC verification using formal analysis and simulation have become must-have techniques in the CDC verification flow.

Recognizing the change in CDC landscape, Cliff Cummings wrote a follow-up paper entitled “Clock Domain Crossing (CDC) Design & Verification Techniques Using SystemVerilog” ², which won the 1^st place award at SNUG 2008.  In this paper, Cliff provided a detailed discussion on problems and solutions in CDC design and verification, and in particular, he mentioned that the industry by then has identified these types of design techniques as clock domain crossing techniques. By 2008, CDC had become a known acronym in the industry and the problem space is also more or less well understood.

However well understood the problem may be, doesn’t mean it is completely solved. Advancement in design size and complexity has created additional requirements in CDC verification in recent years in the areas of performance and capacity. The second-generation tools, though functionally comprehensive, do not meet the needs of technology leaders who are designing multi-million-gate SoC designs with complex clocking architectures. To serve these companies, Real Intent released Meridian CDC 3.0 in 2010, with a focus on capacity and speed so as to enable CDC sign-off. With Meridian CDC 3.0, it is possible to verify over 100 Million gate flat full-chip designs with over 100 clock domains without having to break the design into smaller pieces for CDC verification. This translates into major productivity gains for the design team, and also eliminates the chance of bugs slipping through when stitching results together from sub-blocks. The ability to process a whole 100 Million gate design flat represents a significant improvement over earlier and other solutions.

The past 10 years have seen many changes in CDC design and verification. From a couple of asynchronous clock domains to well over 100 asynchronous clocks, from manual review to the 3^rd generation CDC tools, and the trend is set to continue. Real Intent is a veteran and leader in the field of CDC verification, and will continue to serve the needs of design teams who are pushing the limit of today’s SoC designs as they approach one billion gates.

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¹ Cliff Cummings, “Synthesis and Scripting Techniques for Designing Multi-asynchronous Clock Domains”, http://www.sunburst-design.com/papers/CummingsSNUG2001SJ_AsyncClk.pdf, SNUG-2001.

² Cliff Cummings, “Clock Domain Crossing (CDC) Design & Verification Techniques Using SystemVerilog”, http://www.sunburst-design.com/papers/CummingsSNUG2008Boston_CDC.pdf, SNUG-2008.

A senior executive of one of the big three EDA vendors was once quoted as saying:  “An emulator you used four years ago, you can use as a bookend, but not much else.  Or, you can throw it over the side of a boat and use it to grow coral.”

While we’ve chuckled over this comment for years, we think a better analogy comes from another part of the animal kingdom and it goes something like this:  Traditional hardware emulators are a lot like the dinosaurs that roamed the earth for 160 million years.  Both are now extinct, the latter wiped out at the end of the Mesozoic Era.  The former, wiped out by hardware-assisted verification platforms designed and implemented with the largest commercial FPGAs that are as fast and sleek as a Gazelle.

Dinosaurs were dominant terrestrial vertebrates, a term that sounds slow, plodding and ponderous, not at all unlike the description of early hardware emulators.

At their introduction in the 1980s, emulators were considered revolutionary and a bold feat of engineering marvel.  The high cost of ownership, however, limited adoption to big companies with large budgets and complex design problems.  Further, a traditional emulator’s maximum speed was about one megahertz (MHz), slow even then.  They were also criticized for being difficult to set up, wasting time and resources.  A common refrain in those early days was the excessive time to emulation.

Dinosaurs are known to have laid eggs.  Hmmm.

As we compare the latest generation of hardware emulation systems to the impressive gazelle, it’s easy to understand why they are changing designers’ perception of this market segment.  They perform at significantly faster speeds, are notably dexterous in their design verification deployment, and drastically more cost effective.

Gazelles are reputed to be swift animals.  In fact, some are able to maintain speeds as high as 50 miles per hour for extended periods of time.  Today’s emulation systems are equally swift –– some clock in at 10 megahertz (MHz) on a 40-million gate design.

These new functional verification engines have a small footprint and are light weight, saving space, power and infrastructure costs, and execute at speeds of several megahertz even in transaction-based co-emulation.  Their debugging capabilities are similar to those of the beloved HDL simulator.  Even more attractive is their pricing –– they sell for a fraction of the cost of older generations of emulators.  They can be used by the embedded software team and hardware designers for hardware/software co-verification, and increasingly are used as a solution to an event-based simulator’s runtime problems.

The gazelle is appreciated for being both nimble and graceful, and does not lay eggs.

Experts tell us we can learn much from the Animal Kingdom.  We’ve learned enough to be able to compare and contrast the characteristics of chip verification tools to two venerated animals.  As we’ve shown, traditional emulators have gone the way of the Dinosaur while today’s fast emulation systems are emulating the characteristics of a Gazelle.