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X-FAB: High-temp mission profile

Saturday, September 19th, 2009

Headquartered in Germany, X-FAB is a foundry with manufacturing operations in Erfurt and Dresden, Plymouth in the U.K., Lubbock in Texas, and Kuching, Sarawak in Malaysia. On September 8th, X-FAB made an interesting announcement with the introduction of their XA035 analog/mixed-signal CMOS high-temperature process for ICs that live tough lives: devices that operate in ambient temperatures of up to 175 degrees Celsius in places like the underside of your car.

I had a chance to speak this week by phone about the XA035 process with X-FAB Vice President of Business Development Mark Miller. Miller has a long and distinguished career in EDA with a track record that includes Business Development VP for DFM products at Cadence, VP at TeraSystems and at Synchronicity, and director of the IC Tech Center for Mentor Graphics. These days, Miller’s world is about manufacturing and that’s where our conversation started:

Mark said, “If you look around anyone’s living room, you’ll see a lot of electronics — high-definition TVs, computers, gaming stations, and so on. Our XA035 process, however, is targeted at something different. Of course, the process can be used for ‘standard’ ICs, and for non-volatile memory, [but it also addresses] a wide voltage range that extends beyond the usual digital foundry [offering].

“XA035 is focused on what we call the ‘hidden’ semiconductor markets. Extremely important, these markets include automotive, avionics, and military applications, all of which have as a key attribute the ability to meet stringent qualifications. Interestingly, it’s automotive reliability that involves a lot of such hot and harsh environments, even more so [than some other markets].

“If you’re building a control system in a car, for instance, the electronics have to withstand the underside of a car, where temperatures can go as high as 175 to 185 degrees C. That’s [also the case with] your braking system, another application area where reliability is critical. Just think of a designer being able to use a process technology like XA035, one that meets [industry standard specifications such as] AEC-Q100].

“But, there’s even more in our announcement. If you’re a designer, you also want to be able to analyze your design inside of its [target] environment, along with temperature-qualified models. You want to be able to cycle things 10,000 times or more, to look for dielectric breakdown and stress migration. That requires a lot of extended modeling. Yes, it can be expensive, but if you’re a designer for chips under the hood, you have no choice. Today’s [automotive standards] are not just a list of features, they also include a set of tests and reliability requirement. Most major auto manufacturer [understand this], especially in developing mission critical features.

“It’s outside of [the usual foundry business model] to offer analysis tools, but we have put together a reliability simulator and modeling tool that will take your particular design, establish a mission profile, and then go through and model it for you. The tool [allows you] to understand what the lifetime reliability parameters are, which is a really interesting and novel approach.

“Some products degrade in a step-function failure mode, while others may [exhibit] a gradual decline over a 20-year period. The designers can see all of that with our tools, and therefore understand how to tweak the design to meet the parametric degradation [predicted by the simulation].

“High reliability electronics is a very special applications area. Something a designer develops might be used [in a system] for the next 20 years. As a result, [we see] the designer’s paradox. If you have the responsibility for designing such a product, how do you model it? How many times will it be used. What is the mission profile? With our tools, the designer can take the specifications, and all the models, to get a very clear picture of the reliability. The tool interfaces directly to the device specification and characterizing — it’s pretty unique.”

I asked Mark if analog and mixed-signal devices are more susceptible than digital devices to degradation when deployed in harsh environment.

He said, “It turns out that [in general], the variety of devices manufactured in an analog/mixed-signal foundry is substantially different from what you make in a standard digital-type foundry. We’re not just talking about 3 to 5 volts here. Some of these analog/mixed-signal products [endure] up to 500 or 600 volts. Extensive modeling of those devices [during development] is critical.

“Analog and mixed signal have always been a great deal more work than standard digital. It’s the analog/mixed-signal product that has to interface with the real world. That kind of development requires pretty rigorous engineering and process development.”

I asked Mark if X-FAB headquartered in Germany because of the automotive industry centered there. Mark, who works out of Silicon Valley, said, “Our offering, and the XA035 process in particular, is not specifically an automotive application. In addition to Germany, we also have manufacturing in Malaysia and Texas. X-FAB is very much a global presence, but a lot of the history of the company is centered in Germany.

“There are other independent foundries in the world, but we’ve been in the business for longer than anybody else in analog, mixed-signal [domain]. Working in the general area of high reliability is not new for us.

“The XA035 [really speaks to all of that]: the overall high reliability of devices built on the process, the wide variety of device sizes available including non-volatile memory, and the tools for degradation modeling and developing a mission profile.”

Mark concluded, “There’s a lot of artistry, and creative, innovative design that [characterizes] the analog domain. At X-FAB, we feel that we are very much in that tradition and contributing to its growth.”

The Press Release …

X-FAB Silicon Foundries announced XA035, an analog/mixed-signal CMOS high-temperature foundry process for ICs requiring operating temperatures up to 175 degrees Celsius. The modular 0.35 micrometer process is the first to enable high-temperature-capable SoCs, combining high-voltage and embedded non-volatile memory elements.

Design support includes the XA035 Lifetime Calculator, a tool that calculates expected IC lifetime for a given mission profile to help determine lifetime/temperature trade-offs.

The new XA035 high-temperature process surpasses the stringent AEC-Q100 qualification tests for automotive IC quality and reliability, and is ideally suited for high-precision analog circuits, sensor front-ends, and brushless DC motor controls for automotive, industrial, aerospace and military markets.

X-FAB offers XA035 design kits covering all major EDA platforms. It also features a variety of dense standard cell libraries optimized for area, speed, low power or low noise; and I/O libraries, including ESD support. All libraries take the temperature effects into account. In addition, XA035 supports parasitic diode modeling. This new feature enables pre-layout parasitic diode leakage simulation and lets designers simulate leakages at high temperatures early in the design flow.

Under the Tuscany Sun: From relaxation to collaboration

Tuesday, September 8th, 2009

Tuscany Design Automation, based in Colorado, has been around for over 4 years, but is only now concentrating on making itself known. Part of that process involved bringing EDA veteran Keith Mueller onboard as CEO. Given his long tenure in the industry, Mueller knows full well what it takes to establish a message and the right business model for a successful EDA startup, and by the sounds of things he relishes bringing that knowledge to Tuscany DA.

I spoke by phone with Mueller recently about his background and his new corporate home. He told me that launching a new image and logo for Tuscany was somewhat of a logistical challenge in the 4 short weeks between his arriving at the company in mid-June and DAC 2009 in San Francisco in late July.

“Nonetheless, we pulled it off and had a great response at DAC!” he said.

Mueller added, “Since its inception, the people at Tuscany have been focused on working with early customers to develop tools for structured design and perfecting their core infrastructure and database – focused on the technology, not the messaging. They had never done a press release prior to my joining the company.

“For DAC, we decided to officially launch the structured design tool called Tego, as well as the Tuscany Dashboard, a product with a much broader market built upon their core infrastructure. Tuscany is now definitely on the radar within the industry.

“We’re going to have a broad appeal to those design houses who manage remotely located teams where collaboration is challenging. The Tuscany Dashboard handles the entire gamut of design and physical data, displaying it via the web to the different designers involved, and providing valuable feedback to project managers. It allows everyone on the team, no matter where they’re located, to visualize the design in a way that makes the team completely collaborative and efficient in tracking progress on all fronts. The same model also applies to communications between ASIC vendors and their customers.”

Clearly, Mueller is jazzed about the company. I asked what drew him to Tuscany, given that prior to this involvement he was “retired.”

Mueller said, “They had an extremely talented and committed founding team, which had already survived through the toughest two years in EDA history. They asked me to look at their website and messaging, and I found it suggested a traditional Italian countryside ambiance, relaxing on a patio with a glass of wine overlooking a vineyard. As appealing as that may be, it did not communicate to potential customers the hard-driving nature of the Tuscany technology and team. So, as I came onboard to drive the business end, we worked to modify the image.

“The engineers at Tuscany are providing something that’s really valuable – and yes, it does add some level of Tuscan ‘relaxation’ to the process in that it helps handle the complexity of remotely located teams doing huge designs. More importantly, however, designs will move more quickly and predictably to completion using our technology. That’s the message I wanted to help the company emphasize and develop.

“An additional part of the ‘rebranding’ that we‘ve undertaken since I started in June has been to shorten and modify the original name of the flagship product, Tegula, which refers to an Italian roofing tile. The product is now called Tego, invoking a reference to the same interoperable, structured design associated with Lego building blocks that we’re all familiar with.

“We want people to focus on the fact that our technology helps fit together the disparate parts of a design, and the disparate designers on a team, as easily as Legos fit together. As geometries continue to shrink and design complexity goes off the charts, a structured design methodology becomes more and more critical.”

He added, laughing, “Of course, if design teams and our customers are more relaxed as a result of using our technology, then Tuscany is exactly the right cultural reference.”

A passion for startups …

Keith Mueller has a passion for startups and the out-of-the box creativity such enterprises entail, with a track record of success that includes in reverse chronological order:

* Apache, where he was Employee #8, and served as VP of Worldwide Sales and Marketing, taking the company from $0 to over $20 million in sales during his 4-year tenure prior to his sabbatical in 2006. Mueller noted the company continues to grow, and is primed for additional success as the global and EDA economies improve.

* Silicon Perspective, where Mueller was also Employee #8, also served as VP of Worldwide Sales, and also took the company from $0 to $20 million, prior to its acquisition by Cadence in 2001.

* Anagram, where he was Employee #4, VP of Worldwide Sales, and helped build the company up to the point of its acquisition by Avanti.

* Quickturn, where he was Employee #45, and part of the team that took the company public prior to its acquisition by Cadence.

* Silicon Compilers, back in the late 1980’s, where he started in marketing and developed the foundry relationships that helped customers to compare different process option in terms of die size, power, and speed using the tool called Genesil. Mueller later made the career change into sales, selling that product which allowed designers to work at the micro-architectural level using ALU’s barrel shifters, register files, etc. Silicon Compilers eventually merged with Silicon Design Labs to becomes Silicon Compiler Systems, and was later acquired by Mentor Graphics in 1990.

Mueller said Silicon Compilers was a company ahead of its time, and added, “It’s interesting to me that in many ways, Tuscany is a combination of ideas from both Silicon Compilers and Silicon Perspective.”

Clearly, what Mueller doesn’t know about the dynamics of startups in EDA probably isn’t worth knowing. That’s also the case when it comes to mergers and acquisitions: “I’ve been through 14 M&As in my EDA career. Some have gone more smoothly, or been more successful, than others. but all of them have been memorable. And, all of them have taught me something about the business of EDA, and about myself.”

In the thick of things …

I asked Mueller if rather than heading up Tuscany, shouldn’t he be teaching Startups 101 at a business school at this point his career. He laughed and said, “Maybe, but I’m not done doing startups. I’m not ready to stand on the sidelines and teach others to do it. It’s more fun to be in the thick of the action.

“When I first came out of school, I was an IC designer. That technical background and experience helped me to better understand and relate to the complex job that my customers have to deal with. This background also was of great benefit in my EDA marketing and sales career.

“Now, combining my sales, marketing, and engineering experience, together with the customer input I solicit during my due-diligence process, helps me greatly in identifying the right startup opportunities and team. Certainly there’s an element of luck of being in the right place at the right time, but the nice thing about a startup is that you can truly impact the outcome with a lot of hard work and a willingness to participate in all phases of the business. It’s extremely stimulating.

“After I left Apache, I took 3 years off and had a number of great experiences such as traveling extensively in Africa and New Zealand, getting my instrument pilot rating, and spending quality time with my family. I also did a major remodel of our house during the first 15 months, which was a much more stressful experience than most startups I’ve been in. But, when I saw Tuscany and went through the due diligence of examining the company, it became obvious to me that the underlying quality of the company, the team, and the technology was profound. In my experience, a startup only succeeds when you have strong momentum on all fronts simultaneously – in R&D, in sales, and in management – and we have that at Tuscany.

“We’re competing head-to-head with internally developed solutions and filling a major gap in the offerings of other EDA suppliers. I’m positive that what Tuscany is offering, and will offer in the near future, provides a great deal of value to our customers, and will therefore drive our success and return to investors. This is exactly why I decided to come back out of ‘retirement’ – to enjoy the challenge and stimulation of working at an EDA startup once again.

“Now we’re a team, and I couldn’t be luckier. These folks have been working to carefully preserve their capital as they’ve developed the technology and persevered through this tough economy. I thoroughly believe the company’s now at a point in its trajectory where we can grow, establish and expand on the message, and take the products and the presence to the next phase of growth. It doesn’t get any better than this in terms of timing to be jumping in with both feet.”

Mueller laughed again and said, “Call me crazy, but I’m excited to be back in EDA!”

Car Talk: Wright Stuff, Wrong Speed

Friday, September 4th, 2009

If you missed the opening keynote at Mentor Graphics’ globe-trotting EDA Tech Forum at the Santa Clara Convention Center on September 3rd, you missed hearing from the future of the automobile industry.

Ian Wright, Founder & CEO of Wrightspeed, spoke for an hour on Thursday morning and articulated his vision for the future of electric-drive vehicles. He started by announcing a revolution is at hand, but then spent the next 60 minutes explaining why the migration from combustion-engine vehicles to electric-drive vehicles will take place over the next decade at an evolutionary, not revolutionary pace.

Additionally, and despite the sexiness of the one-off Wrightspeed X1 roadster on full display in the center of the EDA Tech Forum Exhibition Hall, Wright also carefully explained during his keynote address that it’s not the family car, or light-weight, high-performance race cars, where the immediate implementation of electric-drive will succeed.

Instead, Wright said that over the next decade, big old kludgy bread trucks, FedEx delivery vans, and the ubiquitous Number 1 vehicle sold in America, the Ford F1-150, as well as many other types of pick-up trucks, will convert to electric-drive at such a pace that by 2019, upwards of 50 percent of the entire class of “high annual fuel consumption” vehicles and fleets will have left their combustion engines behind.

Per Wright, the tipping point that guarantees the requisite 3-year payback for the cost of converting to electric-drive in big, heavily used, gas-guzzling vehicles is only $3 to $4 per gallon of gasoline. For the “family car”, however, you’ve got to see gas skyrocket to $17 a gallon to defend the economics, and 3-year payback, of transitioning from combustion engine to electric drive.

Hence, fleets of trucks and delivery vans may be distinctly less sexy than roadsters, and designed to meet a far different set of performance metrics, but Ian Wright maintained that it’s these types of work-horse vehicles which will be at the front line of the massive “revolutionary” change to electric drive.

If that’s the case, why does Ian Wright need to show up at engineering conferences like EDA Tech Forum with his speedy X1 in tow? Who cares that his handcrafted vehicle, which looks like a cross between a cantilevered bridge and an old-time go cart, can beat a top-of-the-line Porsche or Ferrari in a classic 0-to-60 mph dust-up?

Well, if you were running a conference and wanted to raffle off a joy ride in a proof-of-concept vehicle, do you think anybody would interested in winning a trip in a FedEx Van? Right. Wright.

Of course, you’d want to raffle off the chance to experience 0-to-60 in 2.9 seconds in a way-cool go-cart, equipped only with shoulder restraints but no visible roll bar.

Also, if your keynote speaker said he was developing “scalable digital drive system platforms”, do you think hundreds of people would show up to hear his talk? Right. Wright.

If, however, your speaker used to work at sexy Tesla Motors, and now heads up Wrightspeed – invoking his own name, and Wilbur & Orville all at the same time – wouldn’t you want Mr. Right to show up with something that made everybody think about Tesla, even if only subliminally?

Okay, enough of all of that. So, what else is Ian Wright’s crystal ball telling him? Per his talk:

* Electric drive is completely, totally going to be the future of the vehicle industry, with the motor driving the wheels directly. Forget the transmission (and, ergo, forget Tesla’s 6831 Li-batteries strapped to same), because sleek, brushless motors (with no more moving parts than 3 ball bearings and a couple of gears) are going to be doing the job, placed right at the wheel.

* Cars are no longer about the magic of superb mechanical design. Going forward, cars will be about the magic of battery systems, electric motors and drive electronics, generator control systems, vehicle dynamic controls, the UI, and software control planes. In other words, cars are going to be about the uber-business model of Wrightspeed.  Forget Detroit. The buzz has moved to Silicon Valley.

* Although the jury’s still out as far as the battery is concerned, Lithium chemistry that will win in the end, as opposed to a host of other contenders including nickel-metal hydride (NiMH). Plus, Lithium’s not an environmental toxin. QED.

* The reason the time frame for conversion to electric-drive should be revolutionary, but is actually evolutionary, is because the national infrastructure and the grid are just not ready. Wright said you can head out from California today, destined for New York, in your combustion-enabled vehicle without worrying about finding gas along the way. If, however, you set out on that same trip in an eVehicle, you should be sure to pack some worry along with the luggage. Where are you going to recharge your eV along the way?

* No matter how much Spectrum and Science Friday may wax poetic over fuel cells in trains or streetcars, the future’s about batteries, batteries, and more batteries. There’s no distribution system in place for Hydrogen, nor any plans to put one there, according to Wright. So, if you don’t like batteries, you’d be far better off putting your money on natural gas, a widely available domestic product, than to go with the sci-fi enthusiasts’ fuel-cell vision of the future.

* Ditto for photovoltaics. There’s just not enough real estate on top of a car, bus, or train to capture the photons needed, especially in places that don’t enjoy the sunny clime of Southern California or Arizona. Of course, if somebody were to produce some kind of breakthrough with the photovoltaic thing, that might change. But, remember: Wright’s talk was all about evolution, not revolution.

So, is it disappointing that the Wright Speed for this evolution is one that recognizes the realities of the engineering challenges and the national infrastructure? Absolutely not, because Ian Wright is the future of the automobile industry. And change takes time.

It also takes money.

Have you got a spare $40 million dollars sitting around? If so, give Ian a call, because you should be hitching your star, your investment dollars, your design expertise, and your vision of the transition to electric-drive to his organization, his system-level design scheme, and his X1 roadster and vision.

The future of the automobile industry is upon us, and Wrightspeed’s going to get there – wherever and whatever there is – a lot faster than anybody else.

In about 2.9 seconds.

Zona Zócalo: All that Zazz

Friday, August 28th, 2009

The Zona Zócalo in Mexico City is the center of action in town. EDA startup Zocalo Tech wants to channel that same energy and become the center of action in Assertion Based Verification. Hence, they’ve recently announced their flagship product, Zazz.

Per the company, “Zazz makes using assertion libraries quick, easy and accurate by automating tedious error prone task with its easy to use, intuitive GUI. With Zazz, the checkers from the most widely used assertion libraries can be attached to a design and documented in minutes.”

In conjunction with the Zazz announcement, I had a chance to chat by phone with Zocalo President Howard Martin. For starters, I asked Martin to give me an update on Assertion Based Verification.

Martin said, “ABV is considered to be the future of verification, but the acceptance has been pretty slow nonetheless. Recently, I looked on John Cooley’s site and found his report from the 2004 SNUG meeting where [Synopsys CEO] Aart de Geus was talking about assertion libraries. De Geus maintained that assertion libraries were going to move the industry forward.”

Martin said that optimism still stands, but added, “There’s a bottleneck that continues to keep ABV from widespread acceptance. Assertions are difficult to create and difficult to reuse – the biggest problem in ABV. Assertions have to be documented, which takes a lot of time. And, there are additional problems depending on whether you‘re looking at the process from the point of view of the designer or that of the verification engineer.

“For the designer, we’re talking about assertion libraries, but libraries are hard to use. Even though Cadence, Mentor, and Synopsys all have libraries that cover up to 100 percent of a designer‘s requirements, they’re not being widely used.  Accellera’s OVL [Open Verification Library] is supposed to be the big answer for creating assertion checkers, but it’s also not being used a lot.

“Instead, people are pushing for designer-provided assertions, but they’re not in widespread use either because it takes a big dent out of a designer’s time to create them. Designers won’t put assertions on a design if it impacts their design time. It’s just too hard. So neither libraries, nor designer-provided assertions are being widely used. Zazz is our solution. It takes these particularly tedious, error-prone tasks and automates them.

“There are approximately 50 different assertion checkers widely used today. With Zazz, we can do any of them in minutes – create them, attach them, create the line statements [in the code]. In fact, of those 50 checkers, 10 of them represent up to 90 percent of the assertions, and we can do those 10 in just 1 minute. Again, everybody agrees that designers should add design checkers, but if it’s a problem to add them, there will be no assertions checkers to check for.”

Martin also explained the issues that plague verification engineer: “If the designer has decided on ABV, the verification engineer has to do the best he can to relate to the assertion checkers. But if the library only cover about 10 percent of the verification engineer’s requirements – if his assertion checkers are at a higher level, at the interface between the block level and the system level, for instance – again there are problems.

“Zazz helps the verification engineer by taking an assertion library and encapsulating it with a GUI that allows him to take the documentation and [facilitate the process]. The result is a great improvement in productivity, and therefore a lower price of design and verification.

“Plus, our tool is not expensive. Our initial offering has a list price for a one-year license of only $5000.”

Clearly Martin is jazzed about Zazz, which prompted a question about the name. He said, “We chose the name Zazz, because it means something that’s outstanding and unique. Something that, the more you have of it, the better you are!

“Nobody so far in EDA has actually been attacking the problem we’re solving at Zocalo with Zazz. In fact, this technology only became an obvious opportunity to us about a year ago. Now we’re happy to say we have our infrastructure in place, the website, and the complete product offering. We’ve completed reams of testing and demos on demand, and really believe we’re bringing something unique to the marketplace – something that will be at the center of ABV.

“There are over 30,000 designers and verification engineers at work around the world today. With Zazz, we can help move the design process up the ladder to the testbench through automatic documentation, plus lessen the difficulties of using SVA [SystemVerilog Assertions]. Previously, SVA has been really tough to use and, as a result, reusability has been zilch.

“If a designer wants to reuse an assertion checker, he needs to go in and cut-and-paste, but the process is such that it’s way too easy to make errors. As a result, designers prefer to use their old assertions and then start over again with their next design.

“With our Zazz technology, however, we’ve hidden the complexity of this type of reuse. We keep track of modifications in the assertions and only update what’s been changed. We also format everything into a structured verification plan, which from the point of the view of the verification engineer is definitely a productivity booster.

“No matter how you look at it, Zazz is very cool!”

Given his enthusiasm, I asked Martin if he thought Zazz could be the next hot product in EDA.

He was quick to reply: “Absolutely! It’s a great, clean product and doesn’t require any interfaces. It supports both versions of Verilog, supports OVL, plus assertion libraries from all three major EDA companies. Zazz will definitely be hot!”

Okay, there it is. Consider yourself been fairly warned. Zocalo Tech has every intention of becoming the center of action in town!

DAC Best Poster & The Voice of the Engineer

Tuesday, August 11th, 2009

Are you sitting down? Are you ready for some astounding news?

Thanks to Tufts EECS Professor Soha Hassoun and the entire DAC Technical Committee, I actually talked to an engineer by phone – two engineers, in fact – without any PR people in on the call. I mean, I actually got to ask questions of real EDA tools users without anybody standing between us.

“What?” you’re asking. “Where? How? Why?”

At DAC this year in San Francisco, a new kind of event debuted, the User Track Poster Session & Ice Cream Social, starting at 1:30 PM on Wednesday, July 29th. I attended along with a lot of other people ranging up and down the wide tunnel that connects North Hall and South Hall in Moscone Center.

Everybody who came got ice cream (actually, it was popsicles), while 38 different teams of EDA tools users and/or vendors and/or gad students stood and entertained questions from the milling masses that wandered in and around the posters. But it didn’t end there.

On Thursday, July 30th, those who attended the DAC Thursday Plenary Session found out which team won the DAC Best Poster Award, a new commendation inaugurated this year that stands alongside the traditional, highly coveted DAC Best Paper Award.

This year’s Best Poster Award went to a team of five, three engineers from Cisco and two from Synopsys, including Ben Chen, Srinath Atluri, Harish Krishnamoorthy, Alex Wakefield, and Balamurugan Veluchamy, for their paper: “Attacking Constraint Complexity in Verification IP Reuse.”

It was Ben Chen and Harish Krishnamoorthy from Cisco that I spoke with by phone.


The August 13th phone call …

Ben – First, I want to thank the Technical Committee from DAC. They put a lot of thought into what kind of papers they selected for presentation. The Poster Session is a very free-flowing process that takes a lot of pressure off of people, but it could use some additional checkpoints. I spoke to Soha Hassoun at DAC and gave her some ideas. She noted them down and said they would help next year to let authors know what to expect.

Q – Can you give me a brief synopsis of your paper?

Ben – We wanted to use real networking case studies that show how to solve specific constraint-random related issues.

Q – With respect to verification, what are your other options if not random?

Harish – You could do directed verification, rather than random, but random hits all combinations and then runs coverage to see what you’ve covered. With directed test cases, however, you’ll always know what features you’re testing.

Q – So random testing is always best?

Harish – No, directed testing is advised, because in random testing it takes a long time to set up the whole environment.

Ben – Both random and directed serve a purpose. We recommend a combination of both, because neither alone is proving to be enough.

Q – Why use networking cases to look at these issues?

Ben – That’s a good question. The direct reason is that we’re Cisco and we do networking ASICs. But, if you take the answer up one level, some of networking problems represent the question: Can you model mathematically some very simple problems that the constraint solver doesn’t have the capacity to solve?

It comes down to a random-ordering problem, a constraint random ordering problem, that can be used in CPU processor verification environments, so some of the problems with the mathematical model are not just restricted to networking.

This is one of the reasons that our paper was a little better received than others at DAC, because it was not just about the networking domain, but pretty much about all processor verification.

Harish – Also, this paper puts more emphasis on scalability. Any industry wants scalable solutions to their problem. Where there is a lot of networking knowledge, and lots of packets and constraints on packets, the problem has a scalable nature and the solution can be put on any processor.

Q – What parameters did you optimize to achieve the ideal design?

Ben – Ideal is not the right word. We’re looking for a more feasible solution, because we’ve simplified the problem into a very simple common mathematical model. Eventually, we did not find a solution just with the tool itself, but found the solution by working with the Synopsys application engineers.

Q – So this is a services solution, more than a product solution?

Ben – Yes.

Q – So some of the congratulations for your award should go to the Synopsys AEs?

Ben – Yes. They were our co-authors on the paper.

Harish – They helped us know what their tool does, but the solution was found because we were able to also know what the tool lacks. To those drawbacks, we added our methodology.

Q – I’ve always thought that a paper that’s too ‘real’ risks giving away the secret sauce of a design team. Is that a problem?

Ben – Yes, if you see it as our paper giving away a competitive edge, for instance, to a Juniper Networks engineer who can then do a better job with their verification work. But we’re not in the business of verification, so we’re not giving away our secret sauce.

Q – But isn’t verification part of what makes a good product?

Ben – Yes, absolutely, but we can compete and still exchange ideas. I compete, for instance, with Harish maybe as a co-worker, so we have a competition. But I don’t hold back some design secret from him [to win].

Q – Sometimes people are skeptical that the tool vendors are the ones who really write the papers, or propose the solutions.

Ben – Yes, that is a perception problem. If you look at some of the papers that were presented at DAC this year in the User Track, you could see some tool pitches. But, we knew that at DAC, and at conference like DVCon and SNUG, the first disqualification for any paper is that it’s a tool pitch. The feedback for our paper was specifically on this issue, because our paper came from the user’s perspective, and provides a user work-around and a practical solution.

Although we were presenting at DAC, we also spent some time at some of the other presenters’ papers and posters. It looks like at least some [of those submissions] were being presented from the tools vendors’ perspective, but ours was [more] from the user’s point of view.

Q – Is this a suggestion for next year for people who wants to submit to this session?

Harish – Yes, don’t be too vendor or tool specific. Our idea was [to submit] something that could be used by anybody, and also to highlight a common problem which basically anyone could run into. Anybody [could be] doing random verification. That’s why we picked it, rather than something [more esoteric].

For next year, [people might want to pick] as a problem something that is generic and relevant to many users, and whether it’s a services or tools solution, something that users ca relate to. [Of course], if it’s a tool solution that solve a lot of user issues, that’s okay.

Q – Do engineers get nervous when they have to make presentations?

Both Harish and Ben laughed.

Ben – Normally, if you hear a presentation [from someone who’s not nervous], there’s a good chance you’re hearing from the marketing people because they’re always smooth. However, we tried to prepare the heck out of our presentation, so if you disqualify our legitimacy because we were not nervous, that would be discouraging.

I’m not ashamed to say that we’re nerds and geeks, so the talking part of presentations is not our strong point. The free-flowing structure of sharing [ideas] at a user track session takes some of the butterflies out of it – especially because we’re so busy from day to day, that taking time to write a whole paper [would] take up a huge chunk of time.

The Poster Session doesn’t require a whole paper, just slides, which makes it a much more relaxed way to share ideas. Writing a full [conference] paper actually discourages users from submitting.

Harish – There is a lot of overhead with writing papers, a heavy workload, versus just making a presentation. A User Track session is just about sharing the ideas.

Q – The poster session seemed really lively at DAC.

Harish – Yes, at the poster session it was possible for people to actually talk to you, and that’s the real purpose of DAC. Yes, there is some marketing attached, but getting to say something to people [is the real purpose].

Ben – The secret is the interaction after the presentation, because it’s that follow-up that defines the Marketing versus Engineering presentation. If you ask Marketing people a question they can’t answer, they would say, “That’s all I know. Talk to an R&D guy.”

An engineer, however, would go on and try to answer your question.

DAC 2009: R U a Wizard of Management Warcraft?

Monday, August 3rd, 2009

Thanks to Virage Logic VP/Chief Scientist Yervant Zorian and Cadence, once again this year those who attended Management Day at DAC were privileged in the final session of the July 28th event to listen in as eight Wizards of Management Warcraft wrapped up a day of individual presentations by talking en masse about their work in an unscripted, unstructured, and boldly spontaneous way.

The 2009 Panel of Wizards included …

* Albert Li – Director, Global Unichip
* Alan Nakamoto – VP Engineering & Founder, PMC-Sierra
* Pierre Garnier – VP & GM Worldwide Wireless Baseband, TI
* Philippe Magarshak – VP Central R&D, STMicroelectronics
* Don Friedberg – Director, Network & Storage Products Group, LSI
* Rani Borkar – VP Digital Enterprise Group, Intel
* Christoph Heer – VP Digital IP & Reuse, Infineon
* Ed Nuckolls – Austin IC R&D, Freescale Semiconductor

Clearly a battle-hardened group of Senior Managers, try as I might as moderator of the panel, I could not break them. Despite my tough and aggressive questions, designed to make these Wizards weep, they simply would not.

Instead, the group remained steadfast, wondrous, and whimsical throughout our conversation, sitting shoulder to shoulder on the stage in front of me, staring down my questions with steely resolve – laughing in the face of the potential for fear, failure, and financial ruin linked to the problems I posed.

Of course, these Wizards had already faced a far tougher audience than I in the hours leading up to our session that day. Covering some of the thorniest problems in IC design, they had already given lengthy presentations on a host of topics …

* Opportunities & Challenges in High-performance Microprocessors (Intel‘s Borkar)
* Opportunities & Trends in 3-D Stacking (STMicro‘s Magarshak)
* Platforms for Next-generation Networking Devices (LSI‘s Friedberg)
* The 5-Month versus 15-Month SOC Development Cycle (PMC-Sierra‘s Nakamoto)
* Design challenges with Intense Mobile Multimedia Processors (TI‘s Garnier)
* IP Development for Complex Wireless Baseband SOCs (Infineon’s Heer)
* EDA for Zero Defect Design (Freescale‘s Nuckolls)
* Trade-off Analysis in Complex SOC Designs (Unichip‘s Li)


Asking, Wanting & Wondering …

Given this fabulous breadth of topics, completely relevant to EDA … 

* You may be asking why all of DAC Land wasn’t in attendance at Management Day. Certainly there were a hundred people in the room for the event, but the thousands who could/should have learned from the Wizards of Management Warcraft were not there. I just don’t know why.

* You may be wanting to see the slides from the presentations. Will they be available anytime soon? I also don’t know, but Yervant Zorian probably does. Contact him at Virage Logic.

* You may be wondering what was left to cover in the closing panel of the day. Thankfully, I do know the answer to that – you’ll find the questions below.

Take a moment to answer the quiz, then compare your results with the Wizards themselves. You’ll find out straightaway if you qualify to join the Club of the Capable, the Federation of the Fierce, the League of Leaders. You’ll find out if you qualify to become …

A Wizard of Management Warcraft!


The Quiz …

1) Which one of you has actually designed anything in the last 12 months?

2) Re: design for manufacturing. Are the tools you need available?

3) Is DFM about tools or about services?

4) Do the foundries withhold information?

5) Are you working at the ESL level?

6) Do you have the third-party tools you need at the ESL level?

7) Do you use any type of Project Management Software?

Eight) Do you buy third-party Project Management Software, or you do develop your own?

9) Do you spend more than 30 minutes a day reading the reports generated by Project Management Software?

10) How do you guarantee that you’re getting information about what’s going on in your organization?

11) Which is a bigger problem for you – the people in the organization you manage, or the people that manage you?

12) What keeps you awake at night – Money/Budgetary issues or Technology issues?

13) Even though some of you already have PhD’s, would you advise a BSEE to go on for an MBA or an MSEE?

14) Do you enjoy your job?

15) Which do you find more compelling about your job – the People or the Technology?


The Answers …

1) Only 1 out of 8 Wizards has done any hands-on design in the last 12 months.

2) 8 out of 8 Wizards said DFM tools are available, but some tools are much harder to use than others.

3) 8 out of 8 Wizards said DFM is about tools, not services. Yet, 8 out of 8 Wizards said they expect a full range of services and assistance from their DFM tool vendors in implementing the tools. They expect their vendors “to put some skin in the game.”

4) 8 out of 8 Wizards said yield and manufacturability data is available from the foundries, but some foundry relationships are better than others. Some foundries are more forthcoming than others.

5) 8 out of 8 Wizards are working today at some level of ESL, but are all still working far more at lower levels of abstraction.

6) 8 out of 8 Wizards said third-party ESL tools are available today, but they all agreed, “The tools are still in their infancy!”

7) 8 out of 8 Wizards use some type of Project Management software.

Eight) 8 out of 8 Wizards use a combination of in-house Project Management software and third-party tools, with a far, far greater reliance on in-house tools over third-party tools.

9) Only 1 Wizard out of 8 spends more than 30 minutes a day reading the reports generated by their Project Management software. Meanwhile, one of the other Wizards said, if a Manager is spending more than 5 minutes a day reading such reports, they don’t really know what’s going on in their organization: “You have to hear directly from your people what’s going on!”

10) 8 out of 8 Wizards said they have a “no-fault” or “open-door” policy that allows information from within their organization to filter up to them, that their people can report on success or failure without fear of recrimination.

11) 4 out of 8 Wizards said the people below them cause them far more headaches than the people above them, but 4 out of 8 Wizards said the people they manage cause them far fewer headaches than the people they themselves have to report to.

12) 7 out of 8 Wizards said the Technology issues make for sleepless nights, far more than Budgetary issues. It’s the Technology, not the Money! Only 1 out of 8 Wizards said it’s the Money.

13) 7 out of 8 Wizards said an MSEE would be far more useful than an MBA. Only 1 out of the 8 said an MBA would be better.

14) 8 out of 8 Wizards said they love their jobs!

15) 7 out of 8 Wizards said it’s absolutely the People that make their jobs worthwhile! Only 1 out of 8 said it’s the Technology.


R U a Wizard?

Do your answers to the quiz correlate with at least 75% of the answers from the Wizards of Management Warcraft?

Well Done!


A Word to the not-Wizards of EDA …

Going forward, future participants in the DAC Big Wig EDA CEO Plenary Session & Panel might take a hint from the courage of the 2009 Wizards of Management Warcraft.

EDA Big Wigs could be Wizards, too, but only if they exhibit willingness to answer unscripted, unvetted questions in public. The idea that EDA companies are publicly traded, and ergo senior management can’t be candid is nonsense. After all, 8 out of 8 of the 2009 Wizards of Management Warcraft work for publicly traded companies.

Enuff said!

DAC: The Whine & Cheese Must-See List

Friday, July 24th, 2009

Enclosed please find two Roadmaps for DAC: First, a suggested schedule of events and sessions to attend at DAC; Then, the “Whine & Cheese Must-See List.” I looking forward to seeing all of you next week at DAC!


DAC: One Journalist’s Plan of Attack …

Saturday, July 25

* Design Automation Summer School

Sunday, July 26

* Tutorials on UML and Multiprocessor Design, plus DFM&Y (events run all day)
* EDAC Reception: Gary Smith Industry Update

Monday, July 27

* Workshop for Bio-design Automation (8 am)
* Workshop for Women in Design Automation (9 am)
* The Young Faculty Workshop (9 am)
* Gary Smith on What’s Hot to Trot at DAC (9:30 am)
* DFM Workshop (all day)
* North American SystemC User Group (1 pm)
* Atrenta Blogfest & Panel: Early Design Closure (2 pm)
* ClioSoft Texas Hold’em (3 pm)
* Pavilion Interview with 2009 MRP Winner Telle Whitney (3:30 pm)
* High Tea with Wally Rhines, Aart de Geus, and Lip-Bu Tan (4:30 pm)
* The DAC Student Design Contest Awards (5 pm)

Tuesday, July 28

* Accellera Breakfast: Scott Sandler moderating (7 am)
* Opening session & TSMC Keynote/EDA Roadmap (8:30 am)
* Pavilion Panel: Software Piracy (10:30 am)
* Co-hosted Lunch Panel: SystemC & TLM-Driven Design versus RTL (11:30 am)
* CEDA Lunch: Research & Education (12 noon)
* IPL Workshop & Lunch: The EDA Earthquake (12 noon)
* Special Session on 22 nanometers (2 pm)
* Pavilion Panel: Interoperable PDKs (2:30 pm)
* Pavilion Panel on Embedded Multicore (3:30)
* Closing Panel for Management Day (4 pm, I’m moderating)
* User Track: Verification (4:30 pm)
* Accellera/SPIRIT: Liberte Fraternite Egalite Reception (6 pm)
* The Denali Party for The Way Cool Quotient (8 pm)

Wednesday, July 29

* WACI Special Session (9 am)
* User Track: Timing Analysis in the Real World (9 pm)
* Exhibition Hall Safari & Journey of Exploration (10 am to 5 pm)
* NVIDIA Keynote: Throughput Computing (11:15 am)
* Pavilion Panel: Green Electronics (12:30 pm)
* User Track: Poster Session & Ice Cream (1:30 pm)
* Special Session: Post-Turing Computation (2 pm)
* Pavilion Panel: Analog/Mixed-Signal ( 3 pm)
* Special Session: Multicore Computing (4:30 pm)
* Technology Panel: Mixed-Signal (4:30 pm)
* Pavilion Panel: Design Reuse (5 pm)
* NASA/ESA Conference on Adaptive Hardware & Systems (co-located w/ DAC)
* DAC Evening Party

Thursday, July 30

* Bug Hunt Special Session (9 am)
* High-School Musical goes High-Tech (10 am)
* Plenary Panel: Wally Rhines on Green Tech (12 noon)
* Tech Panel on Watts — milli & mega (2 pm)
* Special Session: Green Data Centers (4:30 pm)
* User Track: Analog & Mixed-Signal Design (4:30 pm)
* ACM Symposium: Nanoscale Architectures (all day, plus Friday).

Friday, July 31

* Full-day tutorials (there’s an extra fee)
* Two different flavors of Verification
* Parallel Programming
* Nano-everything


About The Whine & Cheese Must-See List …

This week the infamous EDA Cooley (everyone calls him “Cooley” because no one can remember his first name) published the results of his survey where he asked the EDA vendors: What are you showcasing at DAC in San Francisco and what will you be giving away? He got 70 responses and, of course, 65 of them were the usual self-promoting EDA vendor infomercials.

Here instead, you’ll find an alternative list of companies who will also be strutting their stuff next week at DAC — just in case you’re tired of being told by others what’s what in EDA. Included on this Whine & Cheese Must-See List are the names of companies who couldn’t or wouldn’t do what it took to be included on the other list.

I’ve really been working hard to assemble this list, considering everything else I‘ve had going on, so I hope you’ll appreciate it. It includes companies and organizations well worth your time should you visit them in the Exhibition Hall next week at DAC. It’s a good list, although of course, even if a company’s not on this list, it doesn’t mean it’s not worth visiting next week at DAC. But at least with this list, you can be sure that no PR people were disappointed, overworked, or in any other way harmed in assembling the darn thing.


The Whine & Cheese Must-See List

* Accelicon Technologies
* ACCIT – New Systems Research

* Achilles Test Systems
* Altair Engineering
* Altos Design Automation
* Amiq Consulting
* Analog Bits
* AnSyn
* APAC IC Layout Consultant
* Applied Simulation Technology
* Artwork Conversion Software
* Ateeda
* austriamicrosystems
* Avery Design Systems
* BEEcube
* Berkeley Design Automation
* Blue Pearl Software
* Breker Verification Systems
* Cambridge Analog Technologies
* Chipworks
* CoFluent Design
* Concept Engineering
* Coupling Wave Solutions
* CoWare
* CST of America
* Dassault Systemes
* Dataram
* Desaut
* Dolphin Integration
* Dynalith Systems
* EMA Design Automation
* Enterpoint
* Epoch Microelectronics
* Fidus Systems
* FTL Systems
* GateRocket
* Gradient Design Automation
* Helic
* ICDC Partner Pavilion
* Infiniscale
* Infotech Enterprises
* Innovative Logic
* iNoCs
* Instigate
* Interra Systems
* Jspeed Design Automation
* Kilopass Technology
* Legend Design Technology
* Library Technologies
* Logic Perspective Technology
* Lynguent
* Magillem Design Services
* MathWorks
* Micrologic
* Micro Magic
* Mixel
* MunEDA
* NextOp Software
* OptEM Engineering
* Optiwave Systems
* OVM World
* Physware
* PLD Applications
* QThink
* R3 Logic
* Runtime Design Automation
* Satin IP Technologies
* Seloco
* Semifore
* Shearwater Group
* Si2
* SIGDA/DAC University Booth
* Sigrity
* Silicon Design Solutions
* Silicon Image
* SmartPlay Technologies
* SoftJin Technologies
* Sonnet Software
* Spatial
* StarNet Communications
* Synapse Design Automation
* SynTest Technologies
* Teklatech
* Tela Innovations
* The RTC Group
* Tiempo
* TOOL Corp.
* True Circuits
* Test Systems Strategies
* Tuscany Design Automation
* Uniquify
* Univa
* Veritools
* Warthman Associates
* WinterLogic
* Z2 Innovation
* Zeland Software

Semicon, Wally Rhines, & the Top 10 Must-Do’s at DAC

Thursday, July 16th, 2009

A lot of people were at Semicon this week in San Francisco. Organizers were said to be expecting 25,000 for the 38th Annual Gathering of the (hellishly complex) Global Semiconductor Ecosystem, but clearly not everybody showed up.

That’s not to say there weren’t thousands of people in South and North Hall of Moscone Center, but it wasn’t a full house. You could feel it in the eerie calm of the Exhibition Hall – a place traditionally abuzz with seething crowds – and you could see it in the color palette on display. Dark suits. Muted Ties. It was almost funereal, with everybody appearing to be dressed to the nines out of respect for an industry that’s in the direst of straights.

EDAC Chair and Mentor Graphics CEO Wally Rhines gave the Wednesday keynote at Semicon in the Novellus Theater. Rhines was not, however, wearing his darkest suit. It was more like battleship grey. Perhaps Rhines didn’t get the memo: It’s a funeral. More likely, he’s just not as ready as some to give up.


Rhines’ Keynote …

Rhines has been around for a long time. Two decades at TI prior to his last two decades in EDA. He’s seen it all when it comes to boom and bust in semiconductors, and although he did acknowledge in his July 15th keynote that these are the darkest times to date in the history of the industry – with a whopping 56 billion unit volume drop over two quarters, Q4’08/Q1’09, equivalent to the collapse witnessed across a full four quarters in disastrous 2001 – he said this time around it‘s different:

Compared to the previous historic busts in 2001, 1996, and 1985, there was no semiconductor bubble of oversupply and overproduction prior to the current events. Hence, prices will remain more stable and the inevitable recovery will be faster and more deliberate. More importantly, Rhines insisted that Moore’s Law has not collapsed: “The data does not support a slowing of leading edge technologies.” He had lots of graphs on graphs to prove the point.

He also had graphs to prove that, although consolidation is the bellwether of a maturing industry, never over the history of semiconductors have the top 5, or even top 10, companies ever commanded, in aggregate, more than 10-to-15 percent market share. Per Rhines, leading semiconductor companies can never rest on their laurels: “Innovation and cost structures force you to keep up or get out.”

Even more contrarian, Rhines argued the precipitous decline in DRAM prices in recent years should be seen as an example of a positive phenomenon in technology: “As unit prices fall, sales soar [and that] enables innovation in applications.”

Rhines finished his keynote with a brief Q&A. Along with questions about solar technology (the Intersolar North America conference was collocated with Semicon this week), visa restrictions and outsourcing, Rhines was also asked about TSMC’s problems ramping up yield at 40 nanometers.

His response was upbeat to all questions. Rhines shamelessly promoted the Green Technology plenary session at DAC in response to the solar question, said visa restrictions were bad, that outsourcing was good only if it was pursued in search of engineering talent not cost savings, and ended with a ringing endorsement of TSMC. He said, “At all process nodes, yield ramp-up problems are temporary. TSMC will fix it [and move on].”

Rhines ended by insisting that process migration challenges are a great motivator for innovation in EDA. They drive development of new design tools, new place-and-route and verification tools, and provide opportunities for further partnering between EDA vendors and established and/or emerging fabless companies.

When Rhines was done, he got a rousing round of applause for his data-rich keynote, his facility in answering questions across a range of topics, and his palpable optimism – something in short supply at this particular Semicon.


Top 10 Must Do’s at DAC …

After Rhines finished his fantastic (but under-attended) keynote, I headed out to explore Semicon. I ran into an EDA editor in the North Hall who said, given how under-attended Semicon looked in cavernous Moscone Center, DAC housed in that same venue later this month will be a “ghost town.” He told me DAC needs to be folded into Semicon as a technical track.

Following that, I went to the South Hall and saw the Magma, Si2, and Synopsys booths. At Synopsys, I talked at length with Synopsys’ Sr. Director of Marketing, Tom Ferry.

Based on all of that, here are the Top 10 Must Do’s at DAC:

No. 10 – Not as many people are going to show up at DAC as many stakeholders in the EDA industry would like. Get over it.

No. 9 – If you think DAC is going to be a ghost town, don’t come. Go rain on somebody else’s parade.

No. 8Check your cynicism at the door. It’s not helpful, it’s not good for your inner Feng Shui, and it really pisses me off.

No. 7 – Don’t wear a dark suit and muted tie if you are coming to San Francisco. These may be tough times, but it’s not a funeral. It’s DAC. Battleship grey is okay, but bright colors are better.

No. 6 – The Novellus Theater can only be reached by exiting North Hall and turning left on Howard. There’s no foot traffic wandering in from the Exhibit Hall, so if you’re giving a talk there, be prepared for a small turnout.

No. 5 – The world’s gone Gaga over Green. Attend the DAC Thursday Special Plenary Panel, hosted by Wally Rhines: “How Green is My Silicon Valley.”

No. 4 – DAC is not ready to be folded into Semicon. Semicon is for the process, production and test guys, according to Tom Ferry, while DAC is still for designers. Accept it. They’re still two different shows.

Lords of the Samurai

Lords of the Samurai

No. 3 – TSMC has just joined Si2, but is not yet a member of EDAC, although The MathWorks is. Figure out when TSMC will become a member of EDAC.

No. 2 – San Francisco is fabulous, and you’re so lucky to be visiting this month. The DeYoung is hosting King Tut, the Museum of Modern Art is hosting Ansel Adams/Georgia O’Keefe and Richard Avedon, and the Asian Art Museum is hosting the Lords of the Samurai. See at least one of these shows, and let me know which one you saw.

No. 1Learn something new at DAC, something really new! Then write to me and tell me what it is. Make it something positive, thanks. (

No. 0 – Assume this may be your last visit to DAC. Enjoy it like there’s no tomorrow!

ASQED: Get Thee to Kuala Lumpur

Wednesday, July 8th, 2009

Cool stuff’s happening next week in Malaysia as ASQED, the debut edition of Asia ISQED, unfolds in Kuala Lumpur on July 15th and 16th. Conference organizers will welcome 400+ attendees, a 100-percent increase over their initial attendance expectations – very impressive, as other technical conferences in the industry lament decreasing registrations.

When I spoke by phone on July 8th with Ali Iranmanesh, Founder and CEO of Silicon Valley’s ISQED and now Kuala Lumpur’s ASQED, he was preparing to leave for Malaysia and was understandably excited: “There’s definitely a market for [these types of events] in Asia – Malaysia, in particular – where there are multiple fabs, packaging, and design facilities. I expect ASQED will become bigger each year based on the great interest we’re already seeing.”

As proof, Iranmanesh noted the Malaysia Ministry of Innovation has decided to step in as an additional sponsor of the conference (other sponsors include Synopsys, Mentor Graphics, Cadence, and the Malaysia Institute of Microsystems) and has expressed interest in securing Kuala Lumpur as the ASQED venue for at least the next 3 years.

I asked Iranmanesh if other venues in Asia might be of equal interest. He said the enthusiasm of the Malaysian sponsors makes Kuala Lumpur a particularly attractive location for ASQED, as well as the multiple tourist destinations nearby, including beautiful beaches, golf courses, and the iconic Petronas Twin Towers.

Iranmanesh added that Kuala Lupmur’s a balmy 80 degrees with only moderate humidity in July: “It’s a great time of the year to be there.”

Others clearly agree. Per Iranmanesh: “People are coming from Singapore, Korea, Malaysia, India, China, Taiwan and the Middle East. [Recently], many people from these countries have been having difficulty getting to ISQED in Silicon Valley – in particular, many from Asia – due to travel restrictions, visa problems, and financial problems. We’re addressing that need with ASQED, and [a program appropriate] for engineers and upper management.”

To satisfy those audiences, Synopsys President & COO Chi-Foon Chan and University of Tokyo Professor & Solar expert Takashi Tomita are traveling to Kuala Lumpur to give the opening keynotes on July 15th, as well as Verdant Electronics President Joseph Fjelstad, Cadence SVP Charlie Huang, and NXP VP of Research Hans Rijns.

Following these high-profile speakers, ASQED’09 will offer multiple technical tracks, with the majority of the papers coming from Asia (the remainder from the U.S. and Europe). The principle topics of interest, per Iranmanesh, appear to be circuits and systems, design automation methodologies, test and verification, and packaging. Other topics on the program include PCBs, photovoltaic technology, low-power design, and nano/bio-tech. Clearly cool stuff.

So, is it too late for you to get yourself to ASQED in Kuala Lumpur by July 15th? Probably, but there’s always next year. In fact, given the expectations and apparent demand for such conferences in Asia, there may come a time when ASQED becomes the flagship product in the organizers’ portfolio, with ISQED serving as the “satellite campus.” Would the mandate then be, Get Thee to Silicon Valley?  

[Note: Dr. Ali Iranmanesh also serves as Founder, CEO, and Chairman of the Silicon Valley Technical Institute.]

IC Manage & Xuropa – Back to the Future

Friday, July 3rd, 2009

It’s déjà vu all over again here in the summer of 2009.

Once again, bright entrepreneurs are working to deliver on the promise of web-based design,  project management, tool evaluation and sales – James Colgan with his Xuropa website that offers “professional networking, collaboration, marketing and product evaluation tools,” and Dennis Harmon with his IC Manage web-based Global Design Platform management tool that offers “design assembly, derivative management, content delivery, revision control, and release and configuration management.”

Why is it déjà vu? Because over the last 10 years, we’ve heard about these kinds of thing before. Web-based everything was going gang-busters at the end of the 90’s, much less so after the boom busted, and then back on the radar screen with increasing frequency as the overbuilt infrastructure turned out to be useful after all.

Now the conversation’s way past those quaint days. Way, way past. It’s no longer just about or Y2K. Now it’s about SaaS, Cloud Computing, Global Data and Design Management, and Teraflops.

But lest we forget how we got where we are today – the July 2nd Xuropa-Cadence Online Verification Lab announcement (see below), and the recent IC Management Global IC Design Management Report (also see below) that proves people really, truly do want to manage their projects globally – let’s take a (distinctly abbreviated) walk down Memory Lane.

Back to the Future …

June 25, 1999

The buzz builds …

“First Product Developed In Cadence-Synchronicity Technology”

The product was Design Sync (design data management using Synchronicity’s web-based client-server architecture interfaced to Cadence APIs). The partners were Synchronicity and Cadence. Look for quotes from Mike Gianfagna (Cadence).

March 8, 2000

Mike Santarini reporting in EE Times as buzz really builds …

“Monterey launches bold Internet EDA play”

The product was eDolphin (“web version of Dolphin physical design system running remotely on HP machines at the customer’s site or by co-location providers”). The partners were Monterey Design and Hewlett Packard. Look for quotes from Jacques Benkoski (Monterey).

March 28, 2000

Reporting in EE Times as buzz really, really builds …

“Cadence Unveils Its Strategy for the Internet Era”

The initiative was iCadence (“moving EDA to an e-services model … includes Cadence Internet Engineer, Cadence Internet Learning Series,, and”). Look for quotes from Ray Bingham (Cadence).

April 4, 2000

Richard Goering reporting in EE Times as buzz really, really, really builds …

“Cadence crafts new design-oriented site”

The company was SpinCircuit (“web-based supply-chain portal for pc-board market”). The partners were Cadence, HP, and Flextronics. Look for the quotes from Adriaan Lautenberg (Cadence) and Dave De Maria (Cadence), and references to Carly Fiorina (HP), Ray Bingham (Cadence), and Michael Marks (Flextronics).

June 1, 2000

Again, Mike Santarini reporting in EE Times as the buzz becomes manic …

“Synopsys and Avanti roll out virtual design shop

The product was Design Sphere (“open, hosted … fully equipped Internet-based design shop”). The partners were Synopsys, Avanti and TSMC. Look for the quotes from Aart de Geus (Synopsys) and Mark Milligan (Synopsys).

June 1, 2001

Peggy Aycinena reporting in EDAVision Magazine as buzz fades …

“Web-based Design: All the Glitters may be gold”

“Numerous EDA vendors have backed way off of their aggressive development schedules and, in some cases, allowed their web-based design tools to be ‘temporarily’ shelved until the economic conditions re-emerge to support further research and implementation of the products …

“This may be prudent from a short-term financial point of view, but those who are holding back may regret their cautionary stance … Long-term investment in tools that facilitate remote collaboration and IP evaluation is definitely warranted. EDA and IP vendors need to persevere, even in these difficult times.”

Look for quotes in the article from Mike Markowitz (Mentor), Trent Poltronetti (Synchronicity), Daya Nadamuni (Gartner), Bill Alexander (Monterey), Mark Milligan (Synopsys), Dan Holden (TSMC), Peyman Kazemhkani (TSMC), Kuochon Lee (CreOsys), and Mike Curran (Sweetcircuits).

July 2, 2001

John Cooley reporting in EE Times as buzz really fades …

“A Mutating DesignSphere”

Look for the quotes from Bob Wiegand (NxtWave) and Dave Burow (Synopsys).

December 17, 2001

Dave Maliniak reporting in Electronic Design as True Believers soldier on …

“Synchronicity And Cadence Team On IP Management And Reuse Infrastructure”

The products were IPinfraNET and IP Gear. The companies involved were Synchronicity and Cadence. Look for quotes from Dennis Harmon (Synchronicity).

June 8, 2004

Synchronicity sold to MatrixOne …

“MatrixOne Acquires Synchronicity for $18 Million”

Look for quotes from Mark O’Connell (MatrixOne) and Patrick Romich (Synchronicity)

April 23, 2007

Establishing robust web-based project management …

“IC Manage Announces Global Design Platform”

The product is Global Design Platform (streaming TCP, design assembly, derivative
management, real-time delivery, and IT integration using the Perforce engine).

April 29, 2009

The new reality of global management …

“IC Manage Announces Global IC Design Management Report”

Report written by Dennis Harmon (IC Manage).

July  2, 2009

Combining professional networking, collaboration, marketing, and product evaluation …

“Xuropa Launches Online Lab Featuring Cadence Verification IP”

“With only a web browser, approved visitors to Xuropa Online Labs can access the Cadence Incisive MIPI verification IP Components. Users can run simulations, employing them on example circuits … Users can begin to test drive applications in minutes vs. the days or weeks it used to take to get agreements signed, software downloaded, and keys installed.”

The product is Xuropa Online Lab, with partners Xuropa and Cadence. Look for quotes from Susan Peterson (Cadence) and James Colgan (Xuropa).

June 1, 2001

In the spirit of Back to the Future, the last word goes to EDA Vision …

“Web-based Design: All the Glitters may be gold”

“As recently as two years ago, web-based design tools meandered across a range of definitions – anything from e-commerce to application service providers to file management and revisions control. For the current players in EDA and IP, however, web-based design tools are those products that facilitate remote collaboration to a geographically dispersed design team, either across the campus or across the globe, and remote access to IP specifications and evaluation.

“This clarification of the definition of web-based design offers a refreshing ability to focus on a specific end-user and a specific flavor of tool. The get-rich schemes of the Internet Gold Rush may have lost their luster, but the opportunity for long-term profitability in web-based design is greater than ever.”


S2C: FPGA Base prototyping- Download white paper

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