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Archive for August, 2009

Zona Zócalo: All that Zazz

Friday, August 28th, 2009

The Zona Zócalo in Mexico City is the center of action in town. EDA startup Zocalo Tech wants to channel that same energy and become the center of action in Assertion Based Verification. Hence, they’ve recently announced their flagship product, Zazz.

Per the company, “Zazz makes using assertion libraries quick, easy and accurate by automating tedious error prone task with its easy to use, intuitive GUI. With Zazz, the checkers from the most widely used assertion libraries can be attached to a design and documented in minutes.”

In conjunction with the Zazz announcement, I had a chance to chat by phone with Zocalo President Howard Martin. For starters, I asked Martin to give me an update on Assertion Based Verification.

Martin said, “ABV is considered to be the future of verification, but the acceptance has been pretty slow nonetheless. Recently, I looked on John Cooley’s site and found his report from the 2004 SNUG meeting where [Synopsys CEO] Aart de Geus was talking about assertion libraries. De Geus maintained that assertion libraries were going to move the industry forward.”

Martin said that optimism still stands, but added, “There’s a bottleneck that continues to keep ABV from widespread acceptance. Assertions are difficult to create and difficult to reuse – the biggest problem in ABV. Assertions have to be documented, which takes a lot of time. And, there are additional problems depending on whether you‘re looking at the process from the point of view of the designer or that of the verification engineer.

“For the designer, we’re talking about assertion libraries, but libraries are hard to use. Even though Cadence, Mentor, and Synopsys all have libraries that cover up to 100 percent of a designer‘s requirements, they’re not being widely used.  Accellera’s OVL [Open Verification Library] is supposed to be the big answer for creating assertion checkers, but it’s also not being used a lot.

“Instead, people are pushing for designer-provided assertions, but they’re not in widespread use either because it takes a big dent out of a designer’s time to create them. Designers won’t put assertions on a design if it impacts their design time. It’s just too hard. So neither libraries, nor designer-provided assertions are being widely used. Zazz is our solution. It takes these particularly tedious, error-prone tasks and automates them.

“There are approximately 50 different assertion checkers widely used today. With Zazz, we can do any of them in minutes – create them, attach them, create the line statements [in the code]. In fact, of those 50 checkers, 10 of them represent up to 90 percent of the assertions, and we can do those 10 in just 1 minute. Again, everybody agrees that designers should add design checkers, but if it’s a problem to add them, there will be no assertions checkers to check for.”

Martin also explained the issues that plague verification engineer: “If the designer has decided on ABV, the verification engineer has to do the best he can to relate to the assertion checkers. But if the library only cover about 10 percent of the verification engineer’s requirements – if his assertion checkers are at a higher level, at the interface between the block level and the system level, for instance – again there are problems.

“Zazz helps the verification engineer by taking an assertion library and encapsulating it with a GUI that allows him to take the documentation and [facilitate the process]. The result is a great improvement in productivity, and therefore a lower price of design and verification.

“Plus, our tool is not expensive. Our initial offering has a list price for a one-year license of only $5000.”

Clearly Martin is jazzed about Zazz, which prompted a question about the name. He said, “We chose the name Zazz, because it means something that’s outstanding and unique. Something that, the more you have of it, the better you are!

“Nobody so far in EDA has actually been attacking the problem we’re solving at Zocalo with Zazz. In fact, this technology only became an obvious opportunity to us about a year ago. Now we’re happy to say we have our infrastructure in place, the website, and the complete product offering. We’ve completed reams of testing and demos on demand, and really believe we’re bringing something unique to the marketplace – something that will be at the center of ABV.

“There are over 30,000 designers and verification engineers at work around the world today. With Zazz, we can help move the design process up the ladder to the testbench through automatic documentation, plus lessen the difficulties of using SVA [SystemVerilog Assertions]. Previously, SVA has been really tough to use and, as a result, reusability has been zilch.

“If a designer wants to reuse an assertion checker, he needs to go in and cut-and-paste, but the process is such that it’s way too easy to make errors. As a result, designers prefer to use their old assertions and then start over again with their next design.

“With our Zazz technology, however, we’ve hidden the complexity of this type of reuse. We keep track of modifications in the assertions and only update what’s been changed. We also format everything into a structured verification plan, which from the point of the view of the verification engineer is definitely a productivity booster.

“No matter how you look at it, Zazz is very cool!”

Given his enthusiasm, I asked Martin if he thought Zazz could be the next hot product in EDA.

He was quick to reply: “Absolutely! It’s a great, clean product and doesn’t require any interfaces. It supports both versions of Verilog, supports OVL, plus assertion libraries from all three major EDA companies. Zazz will definitely be hot!”

Okay, there it is. Consider yourself been fairly warned. Zocalo Tech has every intention of becoming the center of action in town!

DAC Best Poster & The Voice of the Engineer

Tuesday, August 11th, 2009

Are you sitting down? Are you ready for some astounding news?

Thanks to Tufts EECS Professor Soha Hassoun and the entire DAC Technical Committee, I actually talked to an engineer by phone – two engineers, in fact – without any PR people in on the call. I mean, I actually got to ask questions of real EDA tools users without anybody standing between us.

“What?” you’re asking. “Where? How? Why?”

At DAC this year in San Francisco, a new kind of event debuted, the User Track Poster Session & Ice Cream Social, starting at 1:30 PM on Wednesday, July 29th. I attended along with a lot of other people ranging up and down the wide tunnel that connects North Hall and South Hall in Moscone Center.

Everybody who came got ice cream (actually, it was popsicles), while 38 different teams of EDA tools users and/or vendors and/or gad students stood and entertained questions from the milling masses that wandered in and around the posters. But it didn’t end there.

On Thursday, July 30th, those who attended the DAC Thursday Plenary Session found out which team won the DAC Best Poster Award, a new commendation inaugurated this year that stands alongside the traditional, highly coveted DAC Best Paper Award.

This year’s Best Poster Award went to a team of five, three engineers from Cisco and two from Synopsys, including Ben Chen, Srinath Atluri, Harish Krishnamoorthy, Alex Wakefield, and Balamurugan Veluchamy, for their paper: “Attacking Constraint Complexity in Verification IP Reuse.”

It was Ben Chen and Harish Krishnamoorthy from Cisco that I spoke with by phone.

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The August 13th phone call …

Ben – First, I want to thank the Technical Committee from DAC. They put a lot of thought into what kind of papers they selected for presentation. The Poster Session is a very free-flowing process that takes a lot of pressure off of people, but it could use some additional checkpoints. I spoke to Soha Hassoun at DAC and gave her some ideas. She noted them down and said they would help next year to let authors know what to expect.

Q – Can you give me a brief synopsis of your paper?

Ben – We wanted to use real networking case studies that show how to solve specific constraint-random related issues.

Q – With respect to verification, what are your other options if not random?

Harish – You could do directed verification, rather than random, but random hits all combinations and then runs coverage to see what you’ve covered. With directed test cases, however, you’ll always know what features you’re testing.

Q – So random testing is always best?

Harish – No, directed testing is advised, because in random testing it takes a long time to set up the whole environment.

Ben – Both random and directed serve a purpose. We recommend a combination of both, because neither alone is proving to be enough.

Q – Why use networking cases to look at these issues?

Ben – That’s a good question. The direct reason is that we’re Cisco and we do networking ASICs. But, if you take the answer up one level, some of networking problems represent the question: Can you model mathematically some very simple problems that the constraint solver doesn’t have the capacity to solve?

It comes down to a random-ordering problem, a constraint random ordering problem, that can be used in CPU processor verification environments, so some of the problems with the mathematical model are not just restricted to networking.

This is one of the reasons that our paper was a little better received than others at DAC, because it was not just about the networking domain, but pretty much about all processor verification.

Harish – Also, this paper puts more emphasis on scalability. Any industry wants scalable solutions to their problem. Where there is a lot of networking knowledge, and lots of packets and constraints on packets, the problem has a scalable nature and the solution can be put on any processor.

Q – What parameters did you optimize to achieve the ideal design?

Ben – Ideal is not the right word. We’re looking for a more feasible solution, because we’ve simplified the problem into a very simple common mathematical model. Eventually, we did not find a solution just with the tool itself, but found the solution by working with the Synopsys application engineers.

Q – So this is a services solution, more than a product solution?

Ben – Yes.

Q – So some of the congratulations for your award should go to the Synopsys AEs?

Ben – Yes. They were our co-authors on the paper.

Harish – They helped us know what their tool does, but the solution was found because we were able to also know what the tool lacks. To those drawbacks, we added our methodology.

Q – I’ve always thought that a paper that’s too ‘real’ risks giving away the secret sauce of a design team. Is that a problem?

Ben – Yes, if you see it as our paper giving away a competitive edge, for instance, to a Juniper Networks engineer who can then do a better job with their verification work. But we’re not in the business of verification, so we’re not giving away our secret sauce.

Q – But isn’t verification part of what makes a good product?

Ben – Yes, absolutely, but we can compete and still exchange ideas. I compete, for instance, with Harish maybe as a co-worker, so we have a competition. But I don’t hold back some design secret from him [to win].

Q – Sometimes people are skeptical that the tool vendors are the ones who really write the papers, or propose the solutions.

Ben – Yes, that is a perception problem. If you look at some of the papers that were presented at DAC this year in the User Track, you could see some tool pitches. But, we knew that at DAC, and at conference like DVCon and SNUG, the first disqualification for any paper is that it’s a tool pitch. The feedback for our paper was specifically on this issue, because our paper came from the user’s perspective, and provides a user work-around and a practical solution.

Although we were presenting at DAC, we also spent some time at some of the other presenters’ papers and posters. It looks like at least some [of those submissions] were being presented from the tools vendors’ perspective, but ours was [more] from the user’s point of view.

Q – Is this a suggestion for next year for people who wants to submit to this session?

Harish – Yes, don’t be too vendor or tool specific. Our idea was [to submit] something that could be used by anybody, and also to highlight a common problem which basically anyone could run into. Anybody [could be] doing random verification. That’s why we picked it, rather than something [more esoteric].

For next year, [people might want to pick] as a problem something that is generic and relevant to many users, and whether it’s a services or tools solution, something that users ca relate to. [Of course], if it’s a tool solution that solve a lot of user issues, that’s okay.

Q – Do engineers get nervous when they have to make presentations?

Both Harish and Ben laughed.

Ben – Normally, if you hear a presentation [from someone who’s not nervous], there’s a good chance you’re hearing from the marketing people because they’re always smooth. However, we tried to prepare the heck out of our presentation, so if you disqualify our legitimacy because we were not nervous, that would be discouraging.

I’m not ashamed to say that we’re nerds and geeks, so the talking part of presentations is not our strong point. The free-flowing structure of sharing [ideas] at a user track session takes some of the butterflies out of it – especially because we’re so busy from day to day, that taking time to write a whole paper [would] take up a huge chunk of time.

The Poster Session doesn’t require a whole paper, just slides, which makes it a much more relaxed way to share ideas. Writing a full [conference] paper actually discourages users from submitting.

Harish – There is a lot of overhead with writing papers, a heavy workload, versus just making a presentation. A User Track session is just about sharing the ideas.

Q – The poster session seemed really lively at DAC.

Harish – Yes, at the poster session it was possible for people to actually talk to you, and that’s the real purpose of DAC. Yes, there is some marketing attached, but getting to say something to people [is the real purpose].

Ben – The secret is the interaction after the presentation, because it’s that follow-up that defines the Marketing versus Engineering presentation. If you ask Marketing people a question they can’t answer, they would say, “That’s all I know. Talk to an R&D guy.”

An engineer, however, would go on and try to answer your question.

DAC 2009: R U a Wizard of Management Warcraft?

Monday, August 3rd, 2009

Thanks to Virage Logic VP/Chief Scientist Yervant Zorian and Cadence, once again this year those who attended Management Day at DAC were privileged in the final session of the July 28th event to listen in as eight Wizards of Management Warcraft wrapped up a day of individual presentations by talking en masse about their work in an unscripted, unstructured, and boldly spontaneous way.

The 2009 Panel of Wizards included …

* Albert Li – Director, Global Unichip
* Alan Nakamoto – VP Engineering & Founder, PMC-Sierra
* Pierre Garnier – VP & GM Worldwide Wireless Baseband, TI
* Philippe Magarshak – VP Central R&D, STMicroelectronics
* Don Friedberg – Director, Network & Storage Products Group, LSI
* Rani Borkar – VP Digital Enterprise Group, Intel
* Christoph Heer – VP Digital IP & Reuse, Infineon
* Ed Nuckolls – Austin IC R&D, Freescale Semiconductor

Clearly a battle-hardened group of Senior Managers, try as I might as moderator of the panel, I could not break them. Despite my tough and aggressive questions, designed to make these Wizards weep, they simply would not.

Instead, the group remained steadfast, wondrous, and whimsical throughout our conversation, sitting shoulder to shoulder on the stage in front of me, staring down my questions with steely resolve – laughing in the face of the potential for fear, failure, and financial ruin linked to the problems I posed.

Of course, these Wizards had already faced a far tougher audience than I in the hours leading up to our session that day. Covering some of the thorniest problems in IC design, they had already given lengthy presentations on a host of topics …

* Opportunities & Challenges in High-performance Microprocessors (Intel‘s Borkar)
* Opportunities & Trends in 3-D Stacking (STMicro‘s Magarshak)
* Platforms for Next-generation Networking Devices (LSI‘s Friedberg)
* The 5-Month versus 15-Month SOC Development Cycle (PMC-Sierra‘s Nakamoto)
* Design challenges with Intense Mobile Multimedia Processors (TI‘s Garnier)
* IP Development for Complex Wireless Baseband SOCs (Infineon’s Heer)
* EDA for Zero Defect Design (Freescale‘s Nuckolls)
* Trade-off Analysis in Complex SOC Designs (Unichip‘s Li)

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Asking, Wanting & Wondering …

Given this fabulous breadth of topics, completely relevant to EDA … 

* You may be asking why all of DAC Land wasn’t in attendance at Management Day. Certainly there were a hundred people in the room for the event, but the thousands who could/should have learned from the Wizards of Management Warcraft were not there. I just don’t know why.

* You may be wanting to see the slides from the presentations. Will they be available anytime soon? I also don’t know, but Yervant Zorian probably does. Contact him at Virage Logic.

* You may be wondering what was left to cover in the closing panel of the day. Thankfully, I do know the answer to that – you’ll find the questions below.

Take a moment to answer the quiz, then compare your results with the Wizards themselves. You’ll find out straightaway if you qualify to join the Club of the Capable, the Federation of the Fierce, the League of Leaders. You’ll find out if you qualify to become …

A Wizard of Management Warcraft!

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The Quiz …

1) Which one of you has actually designed anything in the last 12 months?

2) Re: design for manufacturing. Are the tools you need available?

3) Is DFM about tools or about services?

4) Do the foundries withhold information?

5) Are you working at the ESL level?

6) Do you have the third-party tools you need at the ESL level?

7) Do you use any type of Project Management Software?

Eight) Do you buy third-party Project Management Software, or you do develop your own?

9) Do you spend more than 30 minutes a day reading the reports generated by Project Management Software?

10) How do you guarantee that you’re getting information about what’s going on in your organization?

11) Which is a bigger problem for you – the people in the organization you manage, or the people that manage you?

12) What keeps you awake at night – Money/Budgetary issues or Technology issues?

13) Even though some of you already have PhD’s, would you advise a BSEE to go on for an MBA or an MSEE?

14) Do you enjoy your job?

15) Which do you find more compelling about your job – the People or the Technology?

***********************

The Answers …

1) Only 1 out of 8 Wizards has done any hands-on design in the last 12 months.

2) 8 out of 8 Wizards said DFM tools are available, but some tools are much harder to use than others.

3) 8 out of 8 Wizards said DFM is about tools, not services. Yet, 8 out of 8 Wizards said they expect a full range of services and assistance from their DFM tool vendors in implementing the tools. They expect their vendors “to put some skin in the game.”

4) 8 out of 8 Wizards said yield and manufacturability data is available from the foundries, but some foundry relationships are better than others. Some foundries are more forthcoming than others.

5) 8 out of 8 Wizards are working today at some level of ESL, but are all still working far more at lower levels of abstraction.

6) 8 out of 8 Wizards said third-party ESL tools are available today, but they all agreed, “The tools are still in their infancy!”

7) 8 out of 8 Wizards use some type of Project Management software.

Eight) 8 out of 8 Wizards use a combination of in-house Project Management software and third-party tools, with a far, far greater reliance on in-house tools over third-party tools.

9) Only 1 Wizard out of 8 spends more than 30 minutes a day reading the reports generated by their Project Management software. Meanwhile, one of the other Wizards said, if a Manager is spending more than 5 minutes a day reading such reports, they don’t really know what’s going on in their organization: “You have to hear directly from your people what’s going on!”

10) 8 out of 8 Wizards said they have a “no-fault” or “open-door” policy that allows information from within their organization to filter up to them, that their people can report on success or failure without fear of recrimination.

11) 4 out of 8 Wizards said the people below them cause them far more headaches than the people above them, but 4 out of 8 Wizards said the people they manage cause them far fewer headaches than the people they themselves have to report to.

12) 7 out of 8 Wizards said the Technology issues make for sleepless nights, far more than Budgetary issues. It’s the Technology, not the Money! Only 1 out of 8 Wizards said it’s the Money.

13) 7 out of 8 Wizards said an MSEE would be far more useful than an MBA. Only 1 out of the 8 said an MBA would be better.

14) 8 out of 8 Wizards said they love their jobs!

15) 7 out of 8 Wizards said it’s absolutely the People that make their jobs worthwhile! Only 1 out of 8 said it’s the Technology.

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R U a Wizard?

Do your answers to the quiz correlate with at least 75% of the answers from the Wizards of Management Warcraft?

Well Done!

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A Word to the not-Wizards of EDA …

Going forward, future participants in the DAC Big Wig EDA CEO Plenary Session & Panel might take a hint from the courage of the 2009 Wizards of Management Warcraft.

EDA Big Wigs could be Wizards, too, but only if they exhibit willingness to answer unscripted, unvetted questions in public. The idea that EDA companies are publicly traded, and ergo senior management can’t be candid is nonsense. After all, 8 out of 8 of the 2009 Wizards of Management Warcraft work for publicly traded companies.

Enuff said!

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