Thursday's Child

Peggy Aycinena
Peggy Aycinena
Peggy Aycinena is a freelance journalist and Editor of EDA Confidential at www.aycinena.com. She can be reached at peggy at aycinena dot com.

Power and Verification Always Matter

 
June 25th, 2009 by Peggy Aycinena

One day I turned around and found Verification Methodology Manual for Low Power sitting on my desk. To be honest, I have no idea how I came to have this book, if it arrived in the mail or I somehow picked it up at a conference, but I noticed that Synopsys’ Janick Bergeron of Verification Guild fame was one of the authors, so I decided to look though it.

I’m not a verification expert, but as I had already decided to attend the Friday Functional Verification Tutorial on July 31st at DAC, organized by Andy Piziali (which includes Bergeron and IBM’s Avi Ziv), it seemed all the more appropriate to examine the book. Not surprisingly, it turned out to be a great read. At least the first several chapters.

Published in 2009, the authors include – in addition to Bergeron – Synopsys’ Srikanth Jadcherla, Renesas Technology’s Yoshio Inoue, and ARM’s David Flynn. The forward is written by Kelly Larson from Mediatech Wireless and includes this pearl of wisdom: Power always matters.

Previously, I’d been taught to believe: Verification always matters. But after perusing the book, I see the situation is far more complex. Now the reality is: Power and Verification always matter.

So, how do anxious designers go about meeting requisite verification and power goals, when their fundamental tasks are already daunting enough? I wish I could assure you that the authors of VMM for LP offer some comfort, but I cannot. Instead, the authors first give designers many reasons why power management is a problem (Density, Delivery, Leakage, and Lifetime), and then they propose a variety of solutions (including: multi-voltage control, clock gating, back bias, low Vdd standby, multi-rail retention, and state retention with power gating).

Unfortunately, the solutions are actually far more numerous than the previous parenthetical list would indicate, and the VMM for LP authors want designers to know that even when the many strategies are utilized, bugs sometimes creep in. More accurately, bugs always creep in.

Which is why when I got to Chapter 3: Power Management Bugs, my enthusiasm began to wane. There’s just so much to know, so many things to balance, isolate, optimize, minimize, maximize, and consider. It’s clear that “the path to low power design is paved with many errors that are not conventional logic failures [and] they are caused by a variety of reasons.”

Happily, just as I started to despair of mastering the content in VMM for LP, I discoverd Chapter 8: Rules & Guidelines. Exactly what the doctor ordered when it comes to helping designers know what’s what in VMM for LP. Here’s a summary of the concepts:

* Be safe. Don’t transition unless you can.
* Only enable when it’s suitable. Ditto for disable.
* Only use resets that are appropriate.
* Do not wiggle pins.
* Don’t leave fans on if they can be turned off.
* Behavioral models should be accurate.
* Don’t try to open the gate when you come to an Off Island. Jump over the fence.
* Selective anything is good.
* Retention should be specific. Ditto for non-retention.
* Don’t use both edges of the clock. You could hurt somebody.
* Corruption should not be observed.
* Cover all major micros.
* Don’t group registers together if they’re different. They’re not gregarious and don’t mix well.
* Use short broad-spectrum random tests, and tall ones, too – if you can find them.
* Trust, but verify.
* Once verified, don’t modify.

With a sigh of relief, I realized that VMM for LP is not unconquerable. It is instead a user-friendly handbook and tool for anyone who’s designing here in the 21st century. Better yet, having established that power management is tantamount to success in most designs today, and having established a cogent set of rules to achieve that success, the authors of VMM for LP admirably suggest designers re-think  the problem in terms that mere mortals can more easily understand:

Think of a power management scheme in terms of a control system: a system that attempts to regulate the voltage of devices with power and energy as the end functions, and activity, thermal condition, and resource availability as inputs. A control system that has both hardware and software inputs and outputs. The control system view of the power management scheme greatly helps to understand the loop between voltage regulators (voltage sources), power management units (PMU), and functional blocks (controlees).

Exactly.

Clearly, VMM for LP is a companion book to the 2005 best-seller, Verification Methodology Manual for System Verilog (please tell me you already knew that), but the 2009 text is a winner all on its own:

The need for low power design is here to stay,
And the verification issue will not go away.
So if these are your problems, let me be the first to say,
If you’ve got VMM for LP, this is your lucky day.

*********************************
Addendum …

* Density – Amount of power consumed within an area, hence the heat dissipated in an area, which if left unchecked can lead to “fires and explosions.”

* Delivery – Relates to the amount of current that must be delivered at progressively lower supply voltages, and the ability to withstand current fluctuations; worsens as process technologies shrink.

* Leakage – Amount of current consumed by the chip when there’s no activity, which impacts battery life and regulatory issues related to Green design; also worsens with technology shrink.

* Lifetime – Decreasing reliability of chips due to higher current densities and subsequent material degradation.

One Response to “Power and Verification Always Matter”

  1. EDAblogs says:

    Power and verification always matter (http://bit.ly/G7pNr) #46DAC #EDA @paycinena

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