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Peggy Aycinena
Peggy Aycinena
Peggy Aycinena is a freelance journalist and Editor of EDA Confidential at She can be reached at peggy at aycinena dot com.

String of Pearls vs. Web of Wonder

June 18th, 2009 by Peggy Aycinena

When it comes to device physics, there’s a boatload of questions you could ask folks at DAC.

* Why didn’t we stop at 57 or 53.7, when we went from 65 to 45?

* If you stick a stack of die into a tiny plastic package, what does the heat sink look like that shuttles the heat out of the contraption?

* What are the specific electrical properties that distinguish high-k from low-k dielectrics?

* How hot can a laptop get before the devices at the heart of the thing are irreparably harmed, and why?

When it comes to the design flow, however, there’s only one question worth asking.

* Which tools are used, and in what order, to create a chip?

This single question makes any questions regarding device physics look like child’s play, which is why it’s exactly the question I’m setting out to answer when I go to DAC in July. Surely somebody there will have the answer. Surely somebody there will be able to tell me exactly which tools are strung together, end-to-end, to design a chip.

There will be designers at DAC; I’ll ask them. Surely they’ll know.

Better yet, I’ll ask the vendors. Surely they’ll know which tools are used upstream and downstream from their own tools. If I glue their answers together, end-to-end, I’ll get the solution.

Better still, I’ll ask the CAD tool managers. After all, they’re the ones responsible for supporting the flow, for making sure the tools actually work and can interoperate. Surely they’ll tell me. How hard can it be?

Wait – an even better idea. I’ll ask the VCs. They’re such experts, they’ll be able to tell me which tools are used, because they know which companies have market value. Surely they’ll know.

And, what about Senior Management? They love to answer questions. Surely they can answer this one.

So, there you go. I’m coming to DAC with a clipboard and a pen, determined to try to resolve the question although it may not be easy.

After all, it’s the job of the designers to get their chip designed. They’ll use whatever it takes, even if it includes a little tool here and there that they themselves have developed – or, heaven forbid, downloaded off of somebody’s website. The designers may want to keep that sort of thing a secret.

It’s the job of the vendors to provide the tools, and to make sure that John Q. Public thinks their tool is the only tool that can be used at a particular point in the flow: We actually have no competition in our technology niche.

Of course, it’s the job of the CAD guys to keep secrets, as well. If they reveal what string of tools they use, CAD guys from other design houses might copy them. In the world of CAD: String of Tools = Secret Sauce.

VCs and Senior Management? Look, those are the guys who invented NDA. VCs and Senior Management are nothing, if not all about secrets.

So, which tools are used, and in what order, to create a chip? Getting the answer, and the answer itself, is going to be complex.

I suspect I’ll find that the line of tools I’m attempting to unearth isn’t a line at all, but a multi-dimensional mesh of interconnected applications from a wildly interconnected set of vendors that’s devolved over time from a streamlined flow into a rat’s nest of confusion and overlap. I suspect I’ll discover that the answer to my question is not so much a String of Pearls, as a Web of Wonder. More accurately, not so much a String of Pearls as a Web of Bewilderment.

Device physics? Yep, that’s child’s play.

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3 Responses to “String of Pearls vs. Web of Wonder”

  1. Dan Nenni says:

    Hi Peggy,

    I think the most interesting question at DAC will be:

    How do we compete with Synopsys?

    I have mentioned it several times in my blog, I see an EDA monopoly developing that is and will continue to suppress innovation.

    See you at DAC!


  2. Soha Hassoun says:

    Hi Peggy, You ask “Which tools are used, and in what order, to create a chip?”

    There is no better way to find out than actually coming to DAC this year AND attending the new User Track (UT) at DAC.

    All the presentations are by EDA tool users. The speakers include EDA users from Infineon Technologies, Cisco, TI, Xilinx, ST Microelectronics, Intel, Virtutech, ClueLogic, ST Microelectronics, Samsung, Qualcomm, Intel, Fujitsu, IBM, Sun, and others. There are 42 presentations, and 40 posters. The presentations will run Tuesday through Thursday, in parallel to the technical program and exhibits. The poster session is on Wednesday 1:30pm-3pm during DAC.

    I’d also like to stress that all these submissions were evaluated by a committee of expert EDA tool users. So expect your questions to be answered!!

    More information about the User Track can be found at:

    See you at DAC!.. and let’s compare notes.

  3. “I suspect I’ll find that the line of tools I’m attempting to unearth isn’t a line at all, but a multi-dimensional mesh of interconnected applications from a wildly interconnected set of vendors”

    I am not sure it was ever a smooth flow, much less a “string of pearls.”

    I blogged about this recently in “Trends in Project Health” at

    It’s an intelligent mesh, not just a flow.

    There is no longer a sequential design flow in electronic design: there is architectural, layout, and verification exploration. Layout and verification often start before architecture and implementation details are finished. IP blocks further paralellize, loop and interconnect the project flow. With a mesh development, the next extremely difficult question is resource allocation. How do you apply people, machine, licenses, and testing runs? What stage needs more resources? What will be the resource impact on development time, cost and quality?

    One of the key reasons for this is that multiple aspect of the design must be managed in parallel.

    Engineering is managing constraints and trade-offs. A workable plan must balance cost, performance, schedule and quality to develop a useful design. Whole teams are dedicated to power, performance, fault, routing and timing. Each group needs to communicate and escalate optimization and trade-off decisions.

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