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 Decoding Formal

Posts Tagged ‘Vigyan Singhal’

“What if” All Design and Verification Engineers Used Formal?

Monday, November 10th, 2014

What if all design and verification engineers used formal? What if formal tools become smart enough to do the abstractions? What if formal tools had infinite capacity? These and other questions were proposed by attendees on the event survey for this quarter’s Decoding Formal Club event on October 23, 2014 at the Computer History Museum in Mountain View, CA. (more…)

Not Far from Formal to Success

Tuesday, October 7th, 2014

Several acquisitions this year caught my attention, and show the strategic importance of formal verification for chip design.

Proving that formal verification matters, Jasper Design Automation (founded by Oski CEO Vigyan Singhal) was recently acquired by Cadence Design Systems in June, for $170 million. (more…)

Formal Verification, by Everyone and for Everyone

Thursday, September 18th, 2014

You might still be skeptical of the idea that formal verification can be used by everyone. After all, there is a deep-rooted perception in the industry that formal verification is for the elite few formal experts with Ph.Ds.

This might have been true in the early days of formal technology. The formal tools’ capacity was limited and the use model was not mature. So the aid of someone who actually understood the algorithms “under the hood” was important to help the tool solve the tasks at hand.

However, things have changed dramatically in the last decade. (more…)

Oski’s Two New Secure Chambers Support Asia Growth

Wednesday, November 6th, 2013

Oski Technology, founded by Vigyan Singhal, pioneer and practitioner in formal verification, has earned great respect and reputation in the Silicon Valley for helping customers tape out mission-critical projects using formal technology. Leveraging the power of End-to-End formal verification and Abstraction Models, Oski works with its customers to adopt formal sign-off methodology so that formal verification can become part of the verification sign-off flow. (more…)

Oski Technology: Bullish on Formal Verification

Wednesday, October 2nd, 2013

Oski Technology may be named for the famous University of California at Berkeley’s bear mascot, but Oski is not bearish at all on the formal verification market. In fact, it’s downright bullish on this form of verification and its importance to chip design.

One recent morning, Vigyan Singhal, Oski’s president and CEO, was in the Mountain View, Calif., corporate headquarters ready to discuss his life in formal verification and what inspires him and the company he founded. (more…)

Why Formal Can’t Scale without Methodology

Thursday, September 12th, 2013

Formal verification, and in particular model checking, has been around for a few decades now. I found my first post-silicon bug using formal 20 years ago at Motorola Austin in the cache controller block of a PowerPC chip. The power of formal technology drove my Ph.D research and subsequent career in formal verification.

Early on in my career, I focused on developing formal verification tools at Cadence. Later, I founded Jasper and did more of the same. Over the years however, despite the continuous improvement of formal technology, I find that formal adoption has been less than stellar. In particular, I feel people are not harnessing the full power that formal tools can provide. What is needed besides good tools is a scalable methodology.

Methodology is a body of practices, procedures, and rules used in a discipline. In simulation, both open source methodologies e.g. OVM (open verification methodology), UVM (universal verification methodology) and proprietary verification methodologies, internally developed by design teams of a company, exist. These have been of great help to the design and verification communities, which help scale simulation to keep up with the ever increasing complexity of the designs.


Calling All Formal Enthusiasts: Join the Oski “Decoding Formal” Club

Thursday, August 15th, 2013

In our years of providing formal verification services to leading-edge semiconductor companies, I have had the pleasure of meeting and working with many smart and dedicated engineers who paved the way of formal adoption in their companies – studiously applying formal technology to verify more complex designs as well as building up formal methodology so formal can become part of sign-off criteria in their verification flow. I have had countless discussions with these individuals on the nature of formal technology, best practices in formal application, and ways of getting the most out of formal tools in verification. These are valuable mutual learning experiences for all of us.

In working with these formal technologists and practitioners, I have always wanted to create a forum for these kindred spirits – formal enthusiasts, pioneers, leaders and friends who work in different companies but on the same mission. The goal is to promote idea sharing among us so together we can further advance formal technology and broaden formal adoption in the industry.


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