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 Decoding Formal

Posts Tagged ‘Jin Zhang’

“Shift Left” with Formal Technology

Wednesday, April 1st, 2015

“Shift Left” has become a hot phrase after Aart’s keynote speech at DVCon2015 where he talked about how shifting left in schedule resulted from 10x productivity gain in design, IP, verification and software can spur on 100x opportunities in applications across all fields. He suggested many of these technological advances have the potential of changing what mankind is all about.

Static and formal techniques were mentioned as one of the mechanisms that increase productivity and contribute to shift left in the verification schedule. There are several reasons why formal technology is a key driver for the left shift.

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Making the Case to Executives for Formal Verification

Tuesday, February 3rd, 2015

Last year, after my presentation to a customer in Asia, the verification manager said, “You should give this talk to our senior executives, so they understand the benefits of formal.”

It was said in a lighthearted manner, but in reality it rang true. Design and verification engineers and their managers understand the value of formal.  However in order to request funding to promote formal adoption, they still need to make a case to senior executives as to the value of formal. They need compelling arguments, speaking at a strategic level as to why it is critically important and urgent for the company to adopt formal. The list of concerns for senior executives, is long:

  1. Are we staying ahead of competition?
  2. Do our customers have any issues with our products?
  3. Can we deliver our products on schedule and with profit margin?

Funding will become easier, if they understand how formal can address their primary concerns.

To stay ahead of competition not only requires innovative ideas, but also a sharpened toolkit. Semiconductor companies large and small are actively investing in formal adoption so that they have the best verification flow with the most advanced tools and methodologies. There aren’t many formal experts who can do End-to-End formal in the industry. Many companies are paying top dollar to attract formal verification engineers or outsource formal verification tasks for critical projects to the Oski Technology. So if your company doesn’t use formal verification, then this is an easy case to make, in order to catch up with competition.

A post-silicon bug is a nightmare to senior executives. It signifies poor quality, delayed schedule and wasted money. No matter how complex the bug might be at the system level, it resides in one of the design blocks and could have been caught earlier. Using End-to-End formal to achieve sign-off is a sure way to catch corner case bugs early in the flow so as to minimize, or even avoid, post-silicon bugs. So if senior executives are concerned about customer issues with products, the best solution is to incorporate formal in the early stage, for sign-off.

Time is money. Delayed project schedule means extra engineering time and lost potential market opportunity. Formal can reduce project schedule as in the Oski Cisco case study, published at DAC 2011. At the very least with formal, once a property is proven, verification is done. Unlike simulation where reaching the last 20% of coverage closure could take 80% of the time, so there is never a real sense of being complete as it is impossible to simulate all input vectors.

So if adding formal to the flow helps you keep up or stay ahead of competition, avoid post silicon bugs and keep your project schedule in check, it has a big impact for the company.  This should make a strong case to senior execs that formal is something they should hear about – and sponsor – today.

Rob Kurshan, early pioneer and expert in formal verification, speculates here on the future of formal verification in a video interview at a past meeting for the Decoding Formal Club, a forum hosted by Oski Technology for formal enthusiasts, pioneers, leaders and colleagues who work to promote the sharing of ideas and the advancement of formal technology. On February 9 Synopsys is sponsoring the next Decoding Formal Club Meeting about constraints, liveness vs. safety, formal at ARM (and a Klein bottle). Space is limited and pre-registration is required. Sign up here.

New Year’s Resolution – Treading Deep into Formal

Friday, January 16th, 2015

According to statistics published in 2014 by the University of Scranton in Pennsylvania in the Journal of Clinical Psychology, 45% Americans usually make New Year’s Resolutions. And people who explicitly make resolutions are 10 times more likely to attain their goals than people who don’t.

The largest resolution category –– 47%, is related to self-improvement and education. This is me, trying to squeeze time in my busy schedule to work out and keep my brain sharp by learning new things. This year, our family joined a new health club where I can watch TED  Talks as I walk, and I am embarking on a learning journey with my sixth grader on Machine Learning & Robot Design. It has been fun!

As the Director of Marketing at Oski Technology, my New Year’s Resolution for Oski is simple –– Treading Deep into Formal. In the past 18 months, we successfully hosted five Decoding Formal Club events where we, and our invited guests, shared some of the deepest knowledge and practical experiences about formal that cannot be found elsewhere.

We have covered many deep formal topics such as Abstraction ModelsBound AnalysisEnd-to-End Checkers, and Formal Test Planning, all with the goal to achieve Formal Sign-off. Invited guests from industry formal leaders, such as NVIDIA and Broadcom, shared their experiences deploying formal. With deep formal talks, opportunities for formal networking, good food and cool gifts, Decoding Formal Club has become a magnet that attracts formal enthusiasts. It is where deep formal learning happens.

Carrying on the theme of Treading Deep into Formal into 2015, our first Decoding Formal Club meeting will be held Monday, February 9, from 11:30 a.m. until 4:15 p.m. at our usual location, the Computer History Museum in Mountain View.

We have an agenda packed with Deep Formal Talks and lots of fun! It will include talks by:

  • Vigyan Singhal, chief executive officer of Oski Technology, who will share another important topic in Formal Sign-off –– constraint management.
  • NVIDIA Principal Engineer Jon Michelson, co-author of “The Art of Verification with SystemVerilog Assertions” and “The Art of Verification with Vera,” who will present “A Practical Viewpoint on Liveness versus Safety.”
  • Ross Weber, Staff Design Engineer at ARM and author of the best paper award at the Jasper User Group 2014, who will discuss formal achievements at ARM.

While attendees tread deeply into the formal space, we will bring them back with a special invited guest Cliff Stoll. His TED Talk, “The Call to Learn” inspired us to offer one of his Acme Klein Bottles as a giveaway.  And with the Chinese New Year coming February 19, attendees will be in for Chinese flair and other surprises.

The event space can hold only 40 people, and we intentionally keep the event small to offer the best learning and networking experience. Our goal is to make it the best four hours of an attendee’s work week.

Come and join us as we Tread Deep into Formal in 2015. It will be exciting!

Visit the Decoding Formal registration page, here.

Using Formal for Functional Coverage

Wednesday, August 27th, 2014

Brian Bailey’s recent article on “Fixing Functional Coverage” in Semiconductor Engineering (http://semiengineering.com/fixing-functional-coverage/) polled experts from different companies about the challenges of catching all the bugs, utilizing assertions and expanding coverage to the entire system. This blog elaborates on the four points we made in Brian’s article about how formal can help with functional coverage. (more…)

Building Up the Formal Community

Tuesday, April 8th, 2014

In our visits to many of our customers in the past year, we received a few common requests from companies both large and small:

  • Can you help us find formal expertise to hire?
  • Can you train our engineers to become formal experts?
  • Can you help us build an internal formal team – fast?

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Verification Management from a Formal Perspective

Tuesday, February 18th, 2014

Recently, Gabe Moretti, contributing editor to Chip Design, wrote a lengthy article for Systems Design Engineering addressing an important topic, “Verification Management.” It included comments from Atrenta, Breker Verification Systems, Jasper Design Automation, Mentor Graphics, OneSpin Solutions, Oski Technology and Sonics on a series of questions from Gabe on how to manage today’s complex and time-consuming verification process.

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