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Posts Tagged ‘formal verification’

“Shift Left” with Formal Technology

Wednesday, April 1st, 2015

“Shift Left” has become a hot phrase after Aart’s keynote speech at DVCon2015 where he talked about how shifting left in schedule resulted from 10x productivity gain in design, IP, verification and software can spur on 100x opportunities in applications across all fields. He suggested many of these technological advances have the potential of changing what mankind is all about.

Static and formal techniques were mentioned as one of the mechanisms that increase productivity and contribute to shift left in the verification schedule. There are several reasons why formal technology is a key driver for the left shift.

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Making the Case to Executives for Formal Verification

Tuesday, February 3rd, 2015

Last year, after my presentation to a customer in Asia, the verification manager said, “You should give this talk to our senior executives, so they understand the benefits of formal.”

It was said in a lighthearted manner, but in reality it rang true. Design and verification engineers and their managers understand the value of formal.  However in order to request funding to promote formal adoption, they still need to make a case to senior executives as to the value of formal. They need compelling arguments, speaking at a strategic level as to why it is critically important and urgent for the company to adopt formal. The list of concerns for senior executives, is long:

  1. Are we staying ahead of competition?
  2. Do our customers have any issues with our products?
  3. Can we deliver our products on schedule and with profit margin?

Funding will become easier, if they understand how formal can address their primary concerns.

To stay ahead of competition not only requires innovative ideas, but also a sharpened toolkit. Semiconductor companies large and small are actively investing in formal adoption so that they have the best verification flow with the most advanced tools and methodologies. There aren’t many formal experts who can do End-to-End formal in the industry. Many companies are paying top dollar to attract formal verification engineers or outsource formal verification tasks for critical projects to the Oski Technology. So if your company doesn’t use formal verification, then this is an easy case to make, in order to catch up with competition.

A post-silicon bug is a nightmare to senior executives. It signifies poor quality, delayed schedule and wasted money. No matter how complex the bug might be at the system level, it resides in one of the design blocks and could have been caught earlier. Using End-to-End formal to achieve sign-off is a sure way to catch corner case bugs early in the flow so as to minimize, or even avoid, post-silicon bugs. So if senior executives are concerned about customer issues with products, the best solution is to incorporate formal in the early stage, for sign-off.

Time is money. Delayed project schedule means extra engineering time and lost potential market opportunity. Formal can reduce project schedule as in the Oski Cisco case study, published at DAC 2011. At the very least with formal, once a property is proven, verification is done. Unlike simulation where reaching the last 20% of coverage closure could take 80% of the time, so there is never a real sense of being complete as it is impossible to simulate all input vectors.

So if adding formal to the flow helps you keep up or stay ahead of competition, avoid post silicon bugs and keep your project schedule in check, it has a big impact for the company.  This should make a strong case to senior execs that formal is something they should hear about – and sponsor – today.

Rob Kurshan, early pioneer and expert in formal verification, speculates here on the future of formal verification in a video interview at a past meeting for the Decoding Formal Club, a forum hosted by Oski Technology for formal enthusiasts, pioneers, leaders and colleagues who work to promote the sharing of ideas and the advancement of formal technology. On February 9 Synopsys is sponsoring the next Decoding Formal Club Meeting about constraints, liveness vs. safety, formal at ARM (and a Klein bottle). Space is limited and pre-registration is required. Sign up here.

Not Far from Formal to Success

Tuesday, October 7th, 2014

Several acquisitions this year caught my attention, and show the strategic importance of formal verification for chip design.

Proving that formal verification matters, Jasper Design Automation (founded by Oski CEO Vigyan Singhal) was recently acquired by Cadence Design Systems in June, for $170 million. (more…)

Using Formal for Functional Coverage

Wednesday, August 27th, 2014

Brian Bailey’s recent article on “Fixing Functional Coverage” in Semiconductor Engineering (http://semiengineering.com/fixing-functional-coverage/) polled experts from different companies about the challenges of catching all the bugs, utilizing assertions and expanding coverage to the entire system. This blog elaborates on the four points we made in Brian’s article about how formal can help with functional coverage. (more…)

How Long Does It Take to Formally Verify This Design?

Friday, June 13th, 2014

This year at DAC, we asked attendees to participate in a guessing game – make an educated guess about how long it takes to formally verify a design based on the given design description and statistics.

Oski Guessing Game DAC 2014

How Long Does it Take to Formally Verify This Design?

Here is a recap of the information provided to participants:

Design Description

Reorder IP packets that can arrive out of order and dequeue them in order; when an exception occurs, the design flushes the IP packets for which exceptions has occurred. Support 36 different inputs that can send the data for one or more ports. Another interface provides dequeue requests for different ports. Design supports 48 different ports.

Design Interface

Packets arrive with valid signal; a request/grant mechanism for handling requests from 36 different sources; All 36 inputs are independent and can arrive concurrently; All 48 ports can be dequeued in parallel using another request/grant mechanism.

Design Micro-architecture Details

Supports enqueue and dequeue for IP packets for 362 different input and 48 different ports respectively; 48 different queues used to store IP packets for different ports; A round robin arbiter resolves contention between enqueue requests from different sources for the same port at the same cycle. (more…)

Cooley’s Report: Only Half The Story?

Friday, May 23rd, 2014

Every year John Cooley publishes a DAC “must-see” list – a veritable treasure map of good stories. While this list has served DAC attendees in the past, in recent years it has continued to miss an important segment of the ecosystem: the growing number of service providers.

Oski Technology is one such service provider. In fact Oski is the only service provider in the formal verification space, and plays an important role in promoting formal adoption in the industry. Formal can improve verification efficiency and productivity, lead to reduced project cost and shorten time-to-market. Since 2005 we have partnered with many leading semiconductor companies to tape out mission-critical designs and build up their internal formal expertise. (more…)

Building Up the Formal Community

Tuesday, April 8th, 2014

In our visits to many of our customers in the past year, we received a few common requests from companies both large and small:

  • Can you help us find formal expertise to hire?
  • Can you train our engineers to become formal experts?
  • Can you help us build an internal formal team – fast?

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Oski Receives DVCon “Honorable Mention” for Best Paper on Bounded Proofs

Thursday, March 20th, 2014

DVCon 2014 was a terrific show for Oski Technology. Not only were we proud to receive an “Honorable Mention” for (2nd) Best Paper at DVCon “Sign-off with Bounded Formal Verification Proofs”, we had the opportunity to have many meaningful conversations with existing customers and others new to formal verification and eager to learn more about what is possible with formal verification. Our DVCon “Sign-off” paper is available on the Oski Technology Web site. See our DVCon 2014 video here.

DVCon 2014 Oski Technology, Vigyan Singhal

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Serving a Need in the Formal Community

Monday, February 3rd, 2014

Oski Technology launched the quarterly Decoding Formal Club with the goal of creating an industry-wide, independent platform for all formal enthusiasts to share ideas, challenges and solutions so as to advance formal technology and promote formal sign-off in the industry.

On Jan. 23rd 2014, we had our second meeting in the Computer History Museum. 28 formal enthusiasts (many of them formal experts) gathered from 16 different companies including ACM, Broadcom, Cadence, Chelsio, Cisco, Ericsson, Ikanos, Jasper, MediaTek, Mentor Graphics, Microsoft, NVIDIA, Qualcomm, SMI, Synopsys and a stealth startup. Talks were given by Normando Montecillo from Broadcom on data integrity verification and Vigyan Singhal, Oski CEO, on Abstraction Models.

It was a very successful event as demonstrated by the anonymous survey results. Answers to the question “What are your primary goals for attending the event?” reinforced the original intention of the group’s founders, that is to facilitate knowledge sharing and networking among formal experts. (more…)

The Abstraction Model – Is It More, Is It Less?

Wednesday, January 22nd, 2014

Oski Technology provides formal verification services to leading semiconductor companies to verify complex design blocks that are difficult to verify using simulation. In our projects, we often write Abstraction Models to overcome formal complexity barriers that would otherwise render formal verification results inconclusive. For example, for the open-source Sun OpenSparc T1 design, verifying a data transport checker without the Abstraction Models would have taken an estimated 991 days of run-time, but only 147 seconds with the Abstraction Models, a significant speed-up of 600,000X. With Abstraction Models and other similar techniques, formal verification can be used as sign-off criteria in the verification flow; Oski has helped many customers adopt and develop formal sign-off flows.

Customers often have the misconception that Abstraction Models reduce design behaviors which makes the formal verification task easier and allow it to finish sooner. They worry about missing bugs with Abstraction Models. In reality however, Abstraction Models do not reduce design behaviors; to the contrary they add to design behaviors by adding new reset states, and/or state transitions. As a result, no bug will be missed. More is less because when more behaviors are added purposefully and artfully, they can actually make the formal verification job easier for the tools and take less time. This might be counter-intuitive and may take some time and practice to get used to. But if one understands the concept and techniques of writing and using Abstraction Models, formal verification can be put to much better and broader use.

Because each design is different, custom Abstraction Models are needed for each design. There is no Abstraction Model VIP one can purchase to fit all kinds of designs. The good news is that knowing when and how to use Abstraction Models is very much a teachable, learnable skill. We teach our customers about Abstraction Models in our projects and we include the Abstraction Models we develop for the project as source code so customers can write their own Abstraction Models in future projects.

Now is your opportunity to learn more about abstraction models. Vigyan Singhal Oski CEO, will be presenting a talk on Abstraction Models in the upcoming Oski Decoding Formal Club event on Jan. 23rd, 2013 in Mountain View, CA. The talk will cover what Abstraction Models are, when you need them, how to write them and how to use them, using real examples.

Space is limited, so don’t miss this opportunity to come and learn more about Abstraction Models so your formal verification runs will take less time. Register for Oski Decoding Formal Club event on Jan. 23rd, here.

Event: Decoding Formal Club meeting
Date: Thursday January 23, 2014
Time: 1:00 PM – 3:30 PM
Venue: Mountain View, CA.

For Abstraction Models, More is Less!

S2C: FPGA Base prototyping- Download white paper



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