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 Decoding Formal

Posts Tagged ‘best practices formal verification’

Formal Ensures Tight Working Relationships

Wednesday, September 9th, 2015

Gabe Moretti of Chip Design used several points from Jin’s blog post below, in his recent article titled, “Design and Verification Need a Closer Relationship.” The article can be found at:

Today, verification engineers have a whole arsenal in their tool kit in order to combat hidden bugs in the design. Different verification techniques render different working relationship with the designers.

Formal verification is a white-box verification technique, which means formal engineers need to have a good understanding about the internals of the design in order to do effective formal verification. Therefore, formal engineers and RTL designers naturally have a much tighter working relationship than other disciplines.

First, a sound verification methodology should allow equal contribution from all effective techniques, which includes leveraging the exhaustiveness of formal to sign-off on design blocks that are harder to verify with simulation. The block partition between formal and simulation should be clean to simplify the effort on both ends. To achieve that, formal engineers should participate in the architectural planning and exploration stage of design development in order to help influence decisions regarding design partition and block interface. A well-partitioned design with a clean interface will make the decision on where to apply formal, as well as the actual formal verification tasks, much easier.


Building Up the Formal Community

Tuesday, April 8th, 2014

In our visits to many of our customers in the past year, we received a few common requests from companies both large and small:

  • Can you help us find formal expertise to hire?
  • Can you train our engineers to become formal experts?
  • Can you help us build an internal formal team – fast?


Calling All Formal Enthusiasts: Join the Oski “Decoding Formal” Club

Thursday, August 15th, 2013

In our years of providing formal verification services to leading-edge semiconductor companies, I have had the pleasure of meeting and working with many smart and dedicated engineers who paved the way of formal adoption in their companies – studiously applying formal technology to verify more complex designs as well as building up formal methodology so formal can become part of sign-off criteria in their verification flow. I have had countless discussions with these individuals on the nature of formal technology, best practices in formal application, and ways of getting the most out of formal tools in verification. These are valuable mutual learning experiences for all of us.

In working with these formal technologists and practitioners, I have always wanted to create a forum for these kindred spirits – formal enthusiasts, pioneers, leaders and friends who work in different companies but on the same mission. The goal is to promote idea sharing among us so together we can further advance formal technology and broaden formal adoption in the industry.


S2C: FPGA Base prototyping- Download white paper

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