Pippa Slayton is Marketing and Business Development Manager at Oski Technology. She has 8+ years experience in the high-tech industry and drives marketing campaigns, marketing strategy, product launches, social media, and community building and event program management for Oski’s formal … More »
November 10th, 2014 by Pippa Slayton
What if all design and verification engineers used formal? What if formal tools become smart enough to do the abstractions? What if formal tools had infinite capacity? These and other questions were proposed by attendees on the event survey for this quarter’s Decoding Formal Club event on October 23, 2014 at the Computer History Museum in Mountain View, CA. Read the rest of “What if” All Design and Verification Engineers Used Formal?
October 7th, 2014 by Dr. Jin Zhang
Several acquisitions this year caught my attention, and show the strategic importance of formal verification for chip design.
Proving that formal verification matters, Jasper Design Automation (founded by Oski CEO Vigyan Singhal) was recently acquired by Cadence Design Systems in June, for $170 million. Read the rest of Not Far from Formal to Success
September 18th, 2014 by Dr. Jin Zhang
You might still be skeptical of the idea that formal verification can be used by everyone. After all, there is a deep-rooted perception in the industry that formal verification is for the elite few formal experts with Ph.Ds.
This might have been true in the early days of formal technology. The formal tools’ capacity was limited and the use model was not mature. So the aid of someone who actually understood the algorithms “under the hood” was important to help the tool solve the tasks at hand.
However, things have changed dramatically in the last decade. Read the rest of Formal Verification, by Everyone and for Everyone
August 27th, 2014 by Dr. Jin Zhang
Brian Bailey’s recent article on “Fixing Functional Coverage” in Semiconductor Engineering (http://semiengineering.com/fixing-functional-coverage/) polled experts from different companies about the challenges of catching all the bugs, utilizing assertions and expanding coverage to the entire system. This blog elaborates on the four points we made in Brian’s article about how formal can help with functional coverage. Read the rest of Using Formal for Functional Coverage
August 13th, 2014 by Dr. Jin Zhang
The Hardware Model Checking Competition (HWMCC) was conceived at CAV (Computer-Aided Verification) 2006 and first launched at CAV 2007. The goals were to encourage technical advancement of model checking algorithms and thereby their deployment in the industry to promote formal adoption for hardware design verification. Read the rest of Sponsoring Technical Advancement in Formal Verification
June 19th, 2014 by Dr. Jin Zhang
This year at DAC, a question asked repeatedly got our attention: Do you offer advanced formal training program?
While we are not surprised by the request itself, the number, size, type and location of companies that asked about this was surprising. It included a wide spectrum of companies, from the U.S., Japan, Korea, China, along with large companies with established formal teams as well as small start-ups with no formal experience. Even EDA vendors asked if we could do training for them. Read the rest of Formal Training in High Demand
June 13th, 2014 by Dr. Jin Zhang
This year at DAC, we asked attendees to participate in a guessing game – make an educated guess about how long it takes to formally verify a design based on the given design description and statistics.
Here is a recap of the information provided to participants:
May 23rd, 2014 by Dr. Jin Zhang
Every year John Cooley publishes a DAC “must-see” list – a veritable treasure map of good stories. While this list has served DAC attendees in the past, in recent years it has continued to miss an important segment of the ecosystem: the growing number of service providers.
Oski Technology is one such service provider. In fact Oski is the only service provider in the formal verification space, and plays an important role in promoting formal adoption in the industry. Formal can improve verification efficiency and productivity, lead to reduced project cost and shorten time-to-market. Since 2005 we have partnered with many leading semiconductor companies to tape out mission-critical designs and build up their internal formal expertise. Read the rest of Cooley’s Report: Only Half The Story?
May 8th, 2014 by Dr. Jin Zhang
Enter to Win: 1-Week Formal Test Planning Session with Oski Technology
Formal test planning is the first step to ensuring successful End-to-End formal verification and formal sign-off.
There are 3 stages in the process of formal test planning – identifying the right design blocks for formal verification (the where question); estimating the formal verification effort using key metrics (the how much question); and planning the specific formal verification tasks on the chosen designs (the what question).
A good planning session can take several weeks to analyze the design, understand formal complexity hotspots, estimate the effort and craft a workable blueprint for formal verification. However we often see engineers jumping into the act of formal verification without spending enough time in formal test planning. Without proper formal test planning, it is not possible to achieve formal sign-off. Read the rest of Win:1-Week Formal Test Planning Session with Oski Technology
April 8th, 2014 by Dr. Jin Zhang
In our visits to many of our customers in the past year, we received a few common requests from companies both large and small: