Open side-bar Menu
 Decoding Formal

Archive for the ‘Blog’ Category

2015 Just Ahead: “There’s no going back now.”

Monday, December 22nd, 2014

2014 has been an exciting year for advances in technology, and another successful year for Oski Technology.

Applying formal verification technology to the most challenging formal verification problems has been at the core of Oski’s business for nearly 10 years, and in 2014 we continued this journey with customers and partners from more than a dozen companies, many of which are in the top 10 performers in the industry. We expanded our business in Asia by more than 5x, at many new companies whose managers are extremely judicious about where money is being spent in their verification effort.

We continue to balance growth in our customer base with a commitment to advancing the application of formal verification in the industry, by teaching the “how”, as we go. In 2014 we offered advanced formal sign-off training to many of our customers, and have received overwhelmingly positive feedback about how this program has helped these teams navigate the complexity of applying formal verification.

Another important aspect of our commitment to the advancement of the application of formal verification is the user-focused Decoding Formal Club which started out as the Decoding Formal video tutorial series, launched at DAC in 2013. The goal of the Decoding Formal Club is to foster knowledge-sharing about the use of formal verification within the industry. The past few years have seen explosive growth and interest in these events, where we have discussed a range of practical topics of special interest to formal verification engineers, including a popular panel “How to Build a Productive Formal Team” addressing an important question for every manager tasked with adopting formal verification.

We took our June Decoding Formal Club meeting to DAC in San Francisco, in the form of a two-hour DAC Insight tutorial focused on the application of formal test planning, and why it is key to formal sign-off. The most popular videos show highlights from each presentation: “Formal Test Planning”“Formal Test Planning: Case Studies”, and  “Abstraction Models”. Video for the latest event in October 2014, “Formal Talks: Methodology, Application, Real-World Experience”, is here.

The Decoding Formal Club welcomed an impressive array of guest speakers and panelists this year, including Normando Montecillo from Broadcom, Flemming Anderson from Intel, Da Chuang from Memoir Systems (since acquired by Cisco), Prosenjit Chatterjee from NVIDIA, Joanne Ottney from Palo Alto Networks, Syed Suhaib from NVIDIA, and Bob Kurshan, a pioneer of formal verification.

The future for formal verification looks bright, and those at the forefront continue to be optimistic about 2015 and beyond. Bob Kurshan, presenter, states in an interview at the Decoding Formal Club meeting in October 2014, that while there will always be room for simulation, formal will one day be the “workhorse” of verification; others are in strong agreement. Short video interviews featuring Bob Kurshan, Brian Bailey (Semiconductor Engineering), Richard Newton (Ericcson), Kaowen Liu (MediaTek) and Shiva Borzin (OneSpin), and Jin Zhang (Oski Technology), are here. The next meeting is scheduled for February 9, 2015, details to be announced; subscribe here.

With another year behind us, we remain optimistic about the rate at which formal technology is being advanced and adopted. The technology has never moved so fast, as is true of its practical application, especially in the area of end-to-end formal which replaces simulation for verification sign-off. This is an exciting period to be working with formal. We are past the point of no return. As the European Space Agency (ESA) announced during the Rosetta mission, after the Philae lander was released for its trip to the surface of comet 67P, “There’s no going back now.”

Prospects are good that 2015 will be better than ever for technological advances of all kinds. And what better time to say it. “There’s no going back now.”

Happy holidays and best wishes for the New Year!

Oski Technology

P.S. Decode the binary message in the our holiday card (or below), and reply to us at 67P @oskitech.com

01001000 01100001 01110000 01110000 01111001 00100000 01001000 01101111 01101100 01101001 01100100 01100001 01111001 01110011 00100001 

Oski Technology holiday newsletter 2014  01001000 01100001 01110000 01110000 01111001 00100000 01001000 01101111 01101100 01101001 01100100 01100001 01111001 01110011 00100001

[[Begin secret holiday message. End message. Proceed with festivities.]]

Best Wishes for the New Year! "There is no going back now." Philae  P.S Reply to us at 67P@oskitech.com

 

“What if” All Design and Verification Engineers Used Formal?

Monday, November 10th, 2014

What if all design and verification engineers used formal? What if formal tools become smart enough to do the abstractions? What if formal tools had infinite capacity? These and other questions were proposed by attendees on the event survey for this quarter’s Decoding Formal Club event on October 23, 2014 at the Computer History Museum in Mountain View, CA. (more…)

Not Far from Formal to Success

Tuesday, October 7th, 2014

Several acquisitions this year caught my attention, and show the strategic importance of formal verification for chip design.

Proving that formal verification matters, Jasper Design Automation (founded by Oski CEO Vigyan Singhal) was recently acquired by Cadence Design Systems in June, for $170 million. (more…)

Formal Verification, by Everyone and for Everyone

Thursday, September 18th, 2014

You might still be skeptical of the idea that formal verification can be used by everyone. After all, there is a deep-rooted perception in the industry that formal verification is for the elite few formal experts with Ph.Ds.

This might have been true in the early days of formal technology. The formal tools’ capacity was limited and the use model was not mature. So the aid of someone who actually understood the algorithms “under the hood” was important to help the tool solve the tasks at hand.

However, things have changed dramatically in the last decade. (more…)

Using Formal for Functional Coverage

Wednesday, August 27th, 2014

Brian Bailey’s recent article on “Fixing Functional Coverage” in Semiconductor Engineering (http://semiengineering.com/fixing-functional-coverage/) polled experts from different companies about the challenges of catching all the bugs, utilizing assertions and expanding coverage to the entire system. This blog elaborates on the four points we made in Brian’s article about how formal can help with functional coverage. (more…)

Sponsoring Technical Advancement in Formal Verification

Wednesday, August 13th, 2014

The Hardware Model Checking Competition (HWMCC) was conceived at CAV (Computer-Aided Verification) 2006 and first launched at CAV 2007. The goals were to encourage technical advancement of model checking algorithms and thereby their deployment in the industry to promote formal adoption for hardware design verification. (more…)

Formal Training in High Demand

Thursday, June 19th, 2014

This year at DAC, a question asked repeatedly got our attention: Do you offer advanced formal training program?

While we are not surprised by the request itself, the number, size, type and location of companies that asked about this was surprising. It included a wide spectrum of companies, from the U.S., Japan, Korea, China, along with large companies with established formal teams as well as small start-ups with no formal experience. Even EDA vendors asked if we could do training for them. (more…)

How Long Does It Take to Formally Verify This Design?

Friday, June 13th, 2014

This year at DAC, we asked attendees to participate in a guessing game – make an educated guess about how long it takes to formally verify a design based on the given design description and statistics.

Oski Guessing Game DAC 2014

How Long Does it Take to Formally Verify This Design?

Here is a recap of the information provided to participants:

Design Description

Reorder IP packets that can arrive out of order and dequeue them in order; when an exception occurs, the design flushes the IP packets for which exceptions has occurred. Support 36 different inputs that can send the data for one or more ports. Another interface provides dequeue requests for different ports. Design supports 48 different ports.

Design Interface

Packets arrive with valid signal; a request/grant mechanism for handling requests from 36 different sources; All 36 inputs are independent and can arrive concurrently; All 48 ports can be dequeued in parallel using another request/grant mechanism.

Design Micro-architecture Details

Supports enqueue and dequeue for IP packets for 362 different input and 48 different ports respectively; 48 different queues used to store IP packets for different ports; A round robin arbiter resolves contention between enqueue requests from different sources for the same port at the same cycle. (more…)

Cooley’s Report: Only Half The Story?

Friday, May 23rd, 2014

Every year John Cooley publishes a DAC “must-see” list – a veritable treasure map of good stories. While this list has served DAC attendees in the past, in recent years it has continued to miss an important segment of the ecosystem: the growing number of service providers.

Oski Technology is one such service provider. In fact Oski is the only service provider in the formal verification space, and plays an important role in promoting formal adoption in the industry. Formal can improve verification efficiency and productivity, lead to reduced project cost and shorten time-to-market. Since 2005 we have partnered with many leading semiconductor companies to tape out mission-critical designs and build up their internal formal expertise. (more…)

Win:1-Week Formal Test Planning Session with Oski Technology

Thursday, May 8th, 2014

Enter to Win: 1-Week Formal Test Planning Session with Oski Technology

Formal test planning is the first step to ensuring successful End-to-End formal verification and formal sign-off.

There are 3 stages in the process of formal test planning – identifying the right design blocks for formal verification (the where question); estimating the formal verification effort using key metrics (the how much question); and planning the specific formal verification tasks on the chosen designs (the what question).

A good planning session can take several weeks to analyze the design, understand formal complexity hotspots, estimate the effort and craft a workable blueprint for formal verification. However we often see engineers jumping into the act of formal verification without spending enough time in formal test planning. Without proper formal test planning, it is not possible to achieve formal sign-off. (more…)




Internet Business Systems © 2017 Internet Business Systems, Inc.
595 Millich Dr., Suite 216, Campbell, CA 95008
+1 (408)-337-6870 — Contact Us, or visit our other sites:
TechJobsCafe - Technical Jobs and Resumes EDACafe - Electronic Design Automation GISCafe - Geographical Information Services  MCADCafe - Mechanical Design and Engineering ShareCG - Share Computer Graphic (CG) Animation, 3D Art and 3D Models
  Privacy Policy