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 Decoding Formal

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New Year’s Resolution – Treading Deep into Formal

Friday, January 16th, 2015

According to statistics published in 2014 by the University of Scranton in Pennsylvania in the Journal of Clinical Psychology, 45% Americans usually make New Year’s Resolutions. And people who explicitly make resolutions are 10 times more likely to attain their goals than people who don’t.

The largest resolution category –– 47%, is related to self-improvement and education. This is me, trying to squeeze time in my busy schedule to work out and keep my brain sharp by learning new things. This year, our family joined a new health club where I can watch TED  Talks as I walk, and I am embarking on a learning journey with my sixth grader on Machine Learning & Robot Design. It has been fun!

As the Director of Marketing at Oski Technology, my New Year’s Resolution for Oski is simple –– Treading Deep into Formal. In the past 18 months, we successfully hosted five Decoding Formal Club events where we, and our invited guests, shared some of the deepest knowledge and practical experiences about formal that cannot be found elsewhere.

We have covered many deep formal topics such as Abstraction ModelsBound AnalysisEnd-to-End Checkers, and Formal Test Planning, all with the goal to achieve Formal Sign-off. Invited guests from industry formal leaders, such as NVIDIA and Broadcom, shared their experiences deploying formal. With deep formal talks, opportunities for formal networking, good food and cool gifts, Decoding Formal Club has become a magnet that attracts formal enthusiasts. It is where deep formal learning happens.

Carrying on the theme of Treading Deep into Formal into 2015, our first Decoding Formal Club meeting will be held Monday, February 9, from 11:30 a.m. until 4:15 p.m. at our usual location, the Computer History Museum in Mountain View.

We have an agenda packed with Deep Formal Talks and lots of fun! It will include talks by:

  • Vigyan Singhal, chief executive officer of Oski Technology, who will share another important topic in Formal Sign-off –– constraint management.
  • NVIDIA Principal Engineer Jon Michelson, co-author of “The Art of Verification with SystemVerilog Assertions” and “The Art of Verification with Vera,” who will present “A Practical Viewpoint on Liveness versus Safety.”
  • Ross Weber, Staff Design Engineer at ARM and author of the best paper award at the Jasper User Group 2014, who will discuss formal achievements at ARM.

While attendees tread deeply into the formal space, we will bring them back with a special invited guest Cliff Stoll. His TED Talk, “The Call to Learn” inspired us to offer one of his Acme Klein Bottles as a giveaway.  And with the Chinese New Year coming February 19, attendees will be in for Chinese flair and other surprises.

The event space can hold only 40 people, and we intentionally keep the event small to offer the best learning and networking experience. Our goal is to make it the best four hours of an attendee’s work week.

Come and join us as we Tread Deep into Formal in 2015. It will be exciting!

Visit the Decoding Formal registration page, here.

Not Far from Formal to Success

Tuesday, October 7th, 2014

Several acquisitions this year caught my attention, and show the strategic importance of formal verification for chip design.

Proving that formal verification matters, Jasper Design Automation (founded by Oski CEO Vigyan Singhal) was recently acquired by Cadence Design Systems in June, for $170 million. (more…)

Formal Verification, by Everyone and for Everyone

Thursday, September 18th, 2014

You might still be skeptical of the idea that formal verification can be used by everyone. After all, there is a deep-rooted perception in the industry that formal verification is for the elite few formal experts with Ph.Ds.

This might have been true in the early days of formal technology. The formal tools’ capacity was limited and the use model was not mature. So the aid of someone who actually understood the algorithms “under the hood” was important to help the tool solve the tasks at hand.

However, things have changed dramatically in the last decade. (more…)

Using Formal for Functional Coverage

Wednesday, August 27th, 2014

Brian Bailey’s recent article on “Fixing Functional Coverage” in Semiconductor Engineering (http://semiengineering.com/fixing-functional-coverage/) polled experts from different companies about the challenges of catching all the bugs, utilizing assertions and expanding coverage to the entire system. This blog elaborates on the four points we made in Brian’s article about how formal can help with functional coverage. (more…)

Sponsoring Technical Advancement in Formal Verification

Wednesday, August 13th, 2014

The Hardware Model Checking Competition (HWMCC) was conceived at CAV (Computer-Aided Verification) 2006 and first launched at CAV 2007. The goals were to encourage technical advancement of model checking algorithms and thereby their deployment in the industry to promote formal adoption for hardware design verification. (more…)

Formal Training in High Demand

Thursday, June 19th, 2014

This year at DAC, a question asked repeatedly got our attention: Do you offer advanced formal training program?

While we are not surprised by the request itself, the number, size, type and location of companies that asked about this was surprising. It included a wide spectrum of companies, from the U.S., Japan, Korea, China, along with large companies with established formal teams as well as small start-ups with no formal experience. Even EDA vendors asked if we could do training for them. (more…)

How Long Does It Take to Formally Verify This Design?

Friday, June 13th, 2014

This year at DAC, we asked attendees to participate in a guessing game – make an educated guess about how long it takes to formally verify a design based on the given design description and statistics.

Oski Guessing Game DAC 2014

How Long Does it Take to Formally Verify This Design?

Here is a recap of the information provided to participants:

Design Description

Reorder IP packets that can arrive out of order and dequeue them in order; when an exception occurs, the design flushes the IP packets for which exceptions has occurred. Support 36 different inputs that can send the data for one or more ports. Another interface provides dequeue requests for different ports. Design supports 48 different ports.

Design Interface

Packets arrive with valid signal; a request/grant mechanism for handling requests from 36 different sources; All 36 inputs are independent and can arrive concurrently; All 48 ports can be dequeued in parallel using another request/grant mechanism.

Design Micro-architecture Details

Supports enqueue and dequeue for IP packets for 362 different input and 48 different ports respectively; 48 different queues used to store IP packets for different ports; A round robin arbiter resolves contention between enqueue requests from different sources for the same port at the same cycle. (more…)

Cooley’s Report: Only Half The Story?

Friday, May 23rd, 2014

Every year John Cooley publishes a DAC “must-see” list – a veritable treasure map of good stories. While this list has served DAC attendees in the past, in recent years it has continued to miss an important segment of the ecosystem: the growing number of service providers.

Oski Technology is one such service provider. In fact Oski is the only service provider in the formal verification space, and plays an important role in promoting formal adoption in the industry. Formal can improve verification efficiency and productivity, lead to reduced project cost and shorten time-to-market. Since 2005 we have partnered with many leading semiconductor companies to tape out mission-critical designs and build up their internal formal expertise. (more…)

Win:1-Week Formal Test Planning Session with Oski Technology

Thursday, May 8th, 2014

Enter to Win: 1-Week Formal Test Planning Session with Oski Technology

Formal test planning is the first step to ensuring successful End-to-End formal verification and formal sign-off.

There are 3 stages in the process of formal test planning – identifying the right design blocks for formal verification (the where question); estimating the formal verification effort using key metrics (the how much question); and planning the specific formal verification tasks on the chosen designs (the what question).

A good planning session can take several weeks to analyze the design, understand formal complexity hotspots, estimate the effort and craft a workable blueprint for formal verification. However we often see engineers jumping into the act of formal verification without spending enough time in formal test planning. Without proper formal test planning, it is not possible to achieve formal sign-off. (more…)

Building Up the Formal Community

Tuesday, April 8th, 2014

In our visits to many of our customers in the past year, we received a few common requests from companies both large and small:

  • Can you help us find formal expertise to hire?
  • Can you train our engineers to become formal experts?
  • Can you help us build an internal formal team – fast?

(more…)

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