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Jean-Marie Brunet
Jean-Marie Brunet
Jean-Marie Brunet is Sr. Director of Marketing, at Mentor, a Siemens Business. He has served for over 20 years in application engineering, marketing and management roles in the EDA industry, and has held IC design and design management positions at STMicrolectronics, Cadence, and Micron among … More »

Post-silicon SW Debug, AI/ML and SSD Design Verification all at Mentor U2U 2019

May 22nd, 2019 by Jean-Marie Brunet

Mentor U2U in Santa Clara was a particularly interesting event for the emulation division at Mentor. This year, our customers from Marvell, SK hynix, Wave Computing, Broadcom, and AMD talked about their challenges and successes – bringing to other engineers the information they need to apply best practices. If you couldn’t be there in person on May 2, here are a few things to ask yourself.

  • Does the AI/ML design you’re working on need a verification platform that can optimize HW and SW together by running frameworks and performance benchmarks?
  • If you’re designing SSDs, do you want to have access to high-performance memory solutions that allow you to model specific memory types?
  • Are you struggling to reproduce bugs with simulation or FPGA prototyping?
  • When you are doing simulation acceleration, are you faced with the limitations of an interface-based BFM architecture?
  • Are you frustrated by the shortcomings of a verification environment that doesn’t give you the ability to determine memory tuning settings earlier in the design and verification schedule?

If you can relate to any of these questions/topics, I encourage you to check out the presentations from Mentor U2U 2019, Santa Clara. We’re really proud of what our customers are doing to improve their verification strategy by using the Veloce Strato emulation platform. Their challenges give us plenty of reasons to continue working hard to deliver relevant new functionality and features.

Here’s a recap of what was presented and a link to the presentation online.

Marvell“Post-Silicon Software Debug on Veloce Strato,” presented by Rex George, Senior Staff Design Engineer at Marvell.

SK hynix“SSD controller verification with Veloce solutions,” authored by Youngyu Ahn, Senior Engineer at SK hynix.

Wave Computing“Maximizing Veloce Value for AI Design Verification,” authored by Suresh Rajendran, Manager, Hardware Engineering and Edmond Jordon, Director, Hardware Verification Engineering, Wave Computing.

Broadcom“Emulation-ready BFM Architecture using “Tunnel” Interface,” from Prashant Rokade, Hardware Engineer at Broadcom.

AMD“Hybrid Emulation environment for accelerated DRAM bringup,” presented by Russ Hunt, Senior Member Technical Staff at AMD.

Category: Mentor

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