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 Hardware Emulation Journal

Archive for May 22nd, 2019

Post-silicon SW Debug, AI/ML and SSD Design Verification all at Mentor U2U 2019

Wednesday, May 22nd, 2019

Mentor U2U in Santa Clara was a particularly interesting event for the emulation division at Mentor. This year, our customers from Marvell, SK hynix, Wave Computing, Broadcom, and AMD talked about their challenges and successes – bringing to other engineers the information they need to apply best practices. If you couldn’t be there in person on May 2, here are a few things to ask yourself.

  • Does the AI/ML design you’re working on need a verification platform that can optimize HW and SW together by running frameworks and performance benchmarks?
  • If you’re designing SSDs, do you want to have access to high-performance memory solutions that allow you to model specific memory types?
  • Are you struggling to reproduce bugs with simulation or FPGA prototyping?
  • When you are doing simulation acceleration, are you faced with the limitations of an interface-based BFM architecture?
  • Are you frustrated by the shortcomings of a verification environment that doesn’t give you the ability to determine memory tuning settings earlier in the design and verification schedule?

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