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Lauro Rizzatti
Lauro Rizzatti
Verification Consultant & Investor at Oregon Angel Fund

Hardware Emulation Takes on IoT Design Verification

 
December 20th, 2016 by Lauro Rizzatti

I recently read a whitepaper on hardware emulation for the IoT market and captured some thoughts here.  At the end of this article is a link to the entire whitepaper if you want to read more.

IoT captured the semiconductor industry’s attention and the race is on to design chips to support this emerging market. Naturally, IoT chip designs need powerful verification tools, which is why design verification engineers are taking a closer look at hardware emulation. It is the only verification tool to provide capacity, performance and cycles to verify IoT designs.

One hardware emulation platform verifies IoT designs by disconnecting the hardware and operating system from applications that run on the end-user products. Design verification engineers test their designs using applications in the same way they run applications on their electronic devices.

Its OS provides an interface to the emulator for applications that run on top of a single operating system. The OS supports an enterprise server that optimizes resource utilization and provides job management for users to submit jobs from their desktops to emulation resources housed in datacenters. The enterprise server supports concurrent use of the emulator for multiple projects, groups, users and use modes. It determines where to allocate a single or multiple projects to ensure the most efficient use of resources for highly efficient access to datacenter-friendly emulation.

Previously, design verification engineers used emulation in the in-circuit emulation (ICE) mode with peripherals and protocols to exercise their designs. These peripherals and protocols are not software-based. One software tool changed all that, enabling the enterprise server capability, transforming the lab environment into a datacenter with the emulator and workstations to execute software versions of protocol models. It uses the same protocol IP and software stacks as ICE, delivering the same functionality as traditional ICE-based verification with the accuracy of hardware with the flexibility and repeatable results available with software.

Benefits include:

  • Better reliability because it eliminates external hardware and cabling that often introduce faults.
  • Higher productivity through an efficient multi-user environment and the ability to remotely re-configure models by changing their compile parameters, rather than swapping a tangle of external hardware chassis and cables.
  • Lower overall cost utilizing reliable, low-cost workstations for executing software models rather than attaching hardware and testers.
  • Higher return on investment by moving the emulator out of the lab and into the datacenter.
  • Higher quality due to better debug visibility of software-based solutions, giving design verification engineers access to software protocol checkers and analyzers that would be hard to use in a physical environment.

A software-based hardware emulation environment addresses five technological challenges of IoT and network developers –– more protocols per chip, larger and more complex designs, lower power usage requirements, more software and more switch and router ports.

More integration, multi-functionality, multi-processors, and embedded software increase design complexity and the need for hardware emulation.

More integration, multi-functionality, multi-processors, and embedded software increase design complexity and the need for hardware emulation.

Let’s look more closely at why.

Software solutions make it easier to get accurate results because hardware solutions can give different results even with the same stimulus, depending on the state of the hardware. Having a software-based hardware emulation environment for protocols in a design ensures better results.

As designs increase in size, emulation capacity must keep pace. Hardware emulation meets this challenge with a scalable platform.

Hardware emulation is an ideal platform for low-power analysis because it provides a level of accuracy achieved only by running a design in the context of real applications. It has the speed and capacity to boot the OS and run billions of cycles required to fully exercise software applications running on the target hardware.

Software embedded on a chip must be verified at the same time as the hardware. Hardware emulation is thousands or millions of times faster than simulation for larger designs.

Hundred- or thousand-port designs have many connections to hardware all requiring cabling –– not feasible to verify network switch and router designs in an ICE hardware environment. A 128 Ethernet port design, for example, is often hundreds of millions or even billions of gates in size.

Software-based hardware emulation overcomes the obstacles of a hardware environment by moving most of the test environment into software running on a scalable platform that can handle up to two-billion gates. It satisfies all of the objectives of a network switch or router design groups when verifying their chips, including packet latency, bandwidth, packet loss, out-of-order sequences and traffic analysis.

Hardware emulation is flexible, provides more visibility and scales with the increasing capacity and complexity of IoT and network system designs. It supports higher productivity and improves design quality, while delivering most ICE capabilities without additional cables and hardware units. These capabilities and technologies, based on enterprise emulation, reside in a data center accessed remotely, 24 hours a day by multiple groups, users and projects. Hardware emulation delivers software and hardware verification for IoT devices across all IoT markets, providing high-speed verification solutions for multiple protocols, complex designs, accelerated low-power applications and hardware-software debug.

A massive amount of verification is needed to design products that make up the IoT and networking ecosystem. The only way to debug these large, complex designs is with hardware emulation.

For a copy of the whitepaper, go to: http://bit.ly/2h3HHK0

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