Verification Consultant & Investor at Oregon Angel Fund
DVCon Europe 2016 Report: A Rich, Two-Day Technical Program
November 18th, 2016 by Lauro Rizzatti
The 2016 DVCon Europe was held in Munich, Germany, at the Holiday Inns City Center Hotel on October 19-20. This was the third year of the conference and it has a decidedly local focus. In its short life, DVCon Europe has become the leading European event for electronic industry participants, mainly chip and system design verification engineers and managers, to gather and share information on innovative design and verification techniques.
In his opening remarks, Matthias Bauer from Infineon Technologies and Program Chair of the Event, expressed his satisfaction for the record attendance, said to be 20% higher than the previous year.
The two-day program included two keynotes, 16 tutorials, 43 technical papers in 13 sessions, two panels and a presentation at the gala dinner. For this year’s event, the decision was made to eliminate the technical posters. As is its custom, an exhibition hall was setup to give 24 exhibitors the opportunity to display and demo their wares.
UVM, a design verification methodology known as the Universal Verification Methodology, and automotive, as the new frontier for EDA, were the main topics of the conference reflected in the number of tutorials, papers, panels, and one keynote. The breakdown of tutorials and papers are listed hereafter:
- UVM: Five Tutorials and four Papers
- Automotive (Safety, ISO 26262): Three Tutorials and four Papers
- Design Verification and Flows: Three Tutorials and four Papers
- Formal: Two Tutorials and one Paper
- Modeling/Languages: One Tutorial and five Papers
- Low Power Design: One Tutorial and one Paper
- Portable Stimulus: One Tutorial
- Mixed-Signal Verification: Three Papers
I attended a few sessions. In particular, I found the “How Portable Stimulus Addresses Key Verification, Test Reuse, and Portability Challenges” rather informative and well delivered by Larry Melling from Cadence; Staffan Berg of Mentor; Breker’s David Johnson; Adiel Khan at Synopsys; and Karthick Gururaj of Vaynavya Labs.
I also enjoyed the “Designing Safe Cars –– How to Ensure Your Semiconductor Design Meet ISO-26262 Fault-Safety Requirements” by Amir Rahat, VP R&D at Optima Design Automation.
The first keynote was delivered by Hobson Bullman, General Manager of the Technology Services Group at ARM, who is passionate about tools that improve engineering efficiency as an integral part of a solution offering. Hobson described the mission and organization of the newly created Technology Services Group (TSG) to support the computing and tooling requirements to support the billions of new ARM devices built every year. He described trends and practices that maximize development effectiveness across large engineering teams.
The second keynote titled, “The Road Ahead for the Security Connected, Self-Driving Car,” was delivered with brio and interspersed with anecdotes by Juergen Weyer, Vice President of Automotive Sales for EMEA at NXP Semiconductors. He discussed the state of the automotive industry today, the design trends and technologies critical in this market, and highlighted ongoing developments and next-generation solutions to enable securely connected and self-driving cars.
The conference hosted two panels. In one panel, titled “Security in the Automotive Value Chain” and moderated by Joachim Geishauser from NXP, four panelists debated the need for security awareness in the modern design process of automotive components. In particular, the panel discussed security approaches to prevent the breakdown of automotive devices and made an assessment of the status quo. Panelists were Raik Brinkmann from OneSpin, Jurgen Frank of NXP, Mentor’s Joe Hupcey and Frank Vanden Berg from Greenhill.
The second panel was an “Accellera Special Townhall Meeting,” where a few attendees interacted with Accellera board and committee members on current activities and new ideas.
At the gala dinner, Bob Smith, Executive Director of ESD Alliance, previously called EDA Consortium (EDAC), gave a presentation titled “Moore’s Law and the Transition from Chip-Centric Design to System-Level Design.” It focused on the transition from chip-centric design to system-level design. Bob opened the presentation with few critical statistics on the evolution of semiconductor design, and underlined that in 2015 semiconductor IP (SIP) revenues surpassed CAE revenues. He then moved on to explain the multi-die IC technology as the next wave. Described as the transition from integration at the transistor level to integration at the functional or block level, he highlighted the reasons that are driving this move and the benefits that can be achieved.
This year’s DVCon/Europe, hardware emulation, my area of expertise, was virtually absent. It was only mentioned obliquely in few presentations. I urge the steering committee to make it a topic for next year’s discussion because it’s an important piece of the verification puzzle.
In conclusion, 2016 DVCon Europe was a successful event. Are there any other recommendations to improve on it? Few attendees noted that security design in automotive, as critical as it is, did not receive adequate coverage. This was indeed surprising considering that Europe is still leading the automotive industry.