Hardware Emulation Journal
Verification Consultant & Investor at Oregon Angel Fund
Great Ideas, Solid Information Exchange Define DVCon India
September 19th, 2016 by Lauro Rizzatti
Although I don’t want to repeat myself, my 2015 report included my assessment that “the traffic on Bangalore’s roads reminded me of a Circle of Hell from Dante Alighieri’s 14th-century poem, ‘Divine Comedy.’” It was like that again this year. As if this wasn’t enough, the timing of this year’s conference coincided with an unanticipated and unpleasant event.
A little background. Bangalore is the city center of the Karnataka State bordering the Tamil Nadu State. The border is delimited by the river Cauvery that provides crucial and life sustaining water to the two states via a dam. In good years, the dam has enough water to fulfill the needs of both. In bad years, the scarcity of water causes grief, tensions and confrontations. The Summer of 2016 was really bad. I was told that the discord between the two states turned into an enormous political crisis that escalated to the attention of the Prime Minister of India.
The traffic in Bangalore was made worse by this. In fact, until two days before the opening of the conference, the committee was updating attendees with daily bulletins anticipating a possible venue change.
Anyway, the conference took place but attendance was badly affected by the circumstances, figuratively dampening the committee efforts to make it appealing and interesting. Organized over two days, the mornings were filled with keynotes and panels. The afternoons included 11 tutorials on day one and 39 papers on day two. A set of 14 posters lined up an aisle on the premises.
The conference started with a keynote address by Dr. Wally Rhines, Mentor Graphics’ CEO. Titled “Design Verification: Challenging Yesterday, Today, Tomorrow,” Dr. Rhines with his verve and passion presented an overview of the verification landscape since the days of breadboarding via SSI/MSI early ICs. The slides also included data from the 2016 Wilson Research Group Functional Verification Survey of the design community, a recurring effort that dates back to 2007. The trend mentioned last year in the keynote speech by Harry Foster, Mentor Graphics’ chief scientist, was confirmed in the 2016 survey. The Indian engineering community has emerged as the worldwide leader in embracing the SystemVerilog design language and the UVM design methodology.
Dr. Rhines’ keynote was followed by an invited keynote titled “A Make in India Roadmap for System Engineering by RISE Group, IIT Madras,” delivered by professor Kamakoti Veezhinathan from the Indian Institute of Technology Madras. He presented an indigenous project of a RISC-based processor family aiming to power IoT devices all the way to servers.
An invited ESL keynote titled “Microprocessors to Smartphones to Autonomous Cars to Deep Learning” was delivered by Subrangshu Das from Canon India. It overlapped with a DV Keynote by Alok Jain from Cadence titled “Verification for Complex SoCs.”
Two panels on ESL and on DV concluded the first morning. I moderated the DV panel, titled “The Future Verification Flow.” Panelists were Shankar Bhat, Verification and Validation director at Qualcomm India, and Ashish Kumar, senior engineering manager at Broadcom India.
Here is an interesting anecdote: We were originally planning to include a third panelist who had to cancel at the last minute. Before the panel started, the two panelists expressed the concern that without a third panelist, the allocated 40 minutes was too long to fill. I said that we may wrap up earlier to allow attendees to enjoy lunch earlier. After we opened the session, both Shankar and Ashish got deep into the topic, and we ran four minutes over our allotted time.
The discussion included seven questions on the current design flows, from the current state of formal analysis to UVM and emulation and concluded with a near-term forecast. Shankar and Ashish were eager to share their views. I plan a write-up summarizing their views in the next several weeks
The keynote on the second day was delivered by Sushil Gupta, Synopsys’ R&D group director in the Verification Group. After introducing himself as new to Synopys through the Atrenta acquisition, Sushil presented “Today’s SoC Verification Challenges: Mobile and Beyond.” Although interesting, it turned out to be a sales presentation of the entire verification portfolio of Synopsys.
An invited keynote titled “IoT for Smart Cities –– An India Perspective” was delivered by Pamela Kumar, vice president of Cloud Computing Innovation Council of India. It was an impressive talk by a remarkable lady with energy and charisma. In a nutshell, any foreign experience in city planning, while welcome, would be carefully analyzed, though not deployable in India as is. Rather, it would require changes, possibly dramatic, to meet local conditions.
Tutorials, paper and posters covered various aspects of the design and verification processes, from ESL to DV, mostly focused on UVM, low power, and hardware/software co-verification.
Despite the glitch at the start, DVCon India 2016 turned out to be a successful conference, full of great ideas and solid information. As usual, the Indian hosts were gracious.
The 2016 round of DVCon conferences organized by Accellera will conclude with DVCon Europe in Munich, Germany, October 19-20.
The 2017 round will kick-off in San Jose, Calif., February 27-March 2. This will be followed by the inaugural DVCon/China in Shanghai April 19.