2016 DVCon San Jose Report

As customary, the 2016 DVCon/San Jose was held at the DoubleTree Hotel. The dates this year were February 29-March 3.

Attended by approximately 1,200 visitors (about 700 paying customers and 400+ on the free day) and 30 exhibitors, its program included 12 tutorials, 13 technical papers and 45 posters. Topics were on various aspects of design and design verification, with particular emphasis on hardware emulation, Universal Verification Methodology (UVM), portable stimulus, low-power design, and formal.

The event offered a keynote, two panels, one roundtable and three sponsored lunches by each of the three main EDA giants. A conversation between Jim Hogan and Ajoy Bose titled “Crossing the Chasm: From technology to Valuable Enterprise,” was hosted by the EDA Consortium and based on Dr. Bose’s career in building several businesses in the high-tech industry.

The keynote presentation, titled “Design Verification Challenges: Past, Present and Future,” was delivered by Dr. Wally Rhines, Mentor Graphics’ CEO. As always, it was rich in interesting design data covering the evolution of the semiconductor industry from the day of the SSI/MSI devices (circa 1970) to the latest SoC devices (2015). It concluded with a glimpse of the future with emphasis on verification for security and safety. As an avid reader of history, in general, I was fascinated by Wally’s knowledge and excellent memory.

I had the privilege and pleasure to be a panelist on one of the two panels, “Emulation + Static Verification Will Replace Simulation,” moderated by Jim Hogan, from Vista Ventures, and organized by Real Intent’s Graham Bell. Panelists were Ashish Darbari, Imagination Technologies; Richard Ho, Google; Brian Hunter, Cavium; Steven Holloway, Dialog Semiconductor; Pranav Ashar, Real Intent; and me.

Interesting to note, all six panelists, including me, notwithstanding my bias toward emulation, agreed that simulation is here to stay and it will not be replaced by emulation nor by any static verification engine.

In my talking slots I spoke –– may I say “passionately” –– of the critical importance of hardware emulation today. Hardware emulation is a three-decades-old verification technology that is enjoying its primetime thanks to escalating design complexity both in hardware and in embedded software. No other verification engine has the verification breadth and depth of emulation. In fact, it is the only verification technology able to trace a design bug starting in hardware that spreads into the embedded software, or the reverse, making it the most essential verification tool in the tool chest.

Other panelists promoted the revered HDL simulator as an indispensable engine and formal analysis as the new coming-of-age verification tool.

The panel was well attended and, the day after the event, it was described to me as informative and entertaining.

I also was delighted to deliver a technical session titled, “Hardware Emulation: ICE vs Virtual,” sharing the stage with Alex Starr, the emulation guru at AMD. In my intro, I highlighted the evolution of hardware emulation over three decades using a series of tables comparing the state-of-the-art in the early 90s vis-à-vis the latest features and capabilities in today’s emulators. I concluded with my opinion on the future of the technology. Alex brought to the panel the user experience. With a slick and professional presentation full of rich detail, he illustrated the emulation of a GPU design comparing the challenges of ICE versus Virtual.

In conclusion, 2016 DVCon/San Jose was a success and I’m looking toward 2017. Yatin Trivedi, general chair of DVCon, who opened the event with a short introduction, announced the appointment of Mentor’s inimitable Dennis Brophy as the next year’s DVCon general chair. Topics related to the challenges of chip design verification are endless and project teams continue to search for solutions. We can expect another great program with Dennis at the helm.

See you next year! Now, let’s look toward DAC in Austin in June.

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