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 Hardware Emulation Journal

Archive for October, 2015

Project Teams with Massive Networking Chip Designs Turn to Hardware Emulation

Monday, October 26th, 2015

Graphics chips, the longtime champs of massive designs, have lost their title to the new heavyweight, Ethernet switch and router chips, which weigh in at half a billion or more ASIC-equivalent gates.

The complexity of the networking chip stems from a set of unique characteristics such as large number of ports, expanded throughput, decreased latency, and improved security to assure fewer network failures and collisions when packets are transmitted simultaneously.

Just consider the verification plan of a recent Ethernet switch SoC design with a 128-port interface and a variable bandwidth of 1/10/40/100/120Gbps. The project team decided against using an HDL simulator, the traditional and most popular verification tool.


DownStream: Solutions for Post Processing PCB Designs
TrueCircuits: IoTPLL

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