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Lauro Rizzatti
Lauro Rizzatti
Verification Consultant & Investor at Oregon Angel Fund

DVCon India –– The Jewel of the Crown

 
September 21st, 2015 by Lauro Rizzatti

Many PBS stations in the U.S. are promoting the rebroadcast of the 1984 series “The Jewel of the Crown.” A jewel in the crown was my sentiment about the recent DVCon India, one of several design and verification conferences organized by the industry standards organization Accellera Systems Initiative.

DVCon India was held in Bangalore September 10-11. With an attendance of 650 versus 400 in 2014, it was held in the Leela Palace, a significantly larger venue than last year’s Hotel Park Plaza.

All in all, it was a great conference, full of substance information and great people in an attractive facility, if one can overlook the road traffic. It reminded me of a Circle of Hell from Dante Alighieri’s 14th-century poem, “Divine Comedy.”

The conference coincided with the 10th anniversary of the SystemVerilog and Universal Verification Methodology (UVM) standardization by IEEE. In two sessions, Dennis Brophy, Accellera’s Director and Vice Chairman, and Yatin Trivedi, Accellera’s Director and Treasurer, took the stage to highlight the standards evolution from the early days of Open Verilog International (OVI) circa 1990 and later, VHDL International (VI). OVI and VI merged in 2000 to form Accellera.

DVCon India kicked off with a keynote address by Harry Foster, Chief Scientist for Mentor Graphics’ Design Verification Technology Division. Titled “From Growing Complexity to Faster Horses,” Harry presented results of the 2014 Wilson Research Group Functional Verification Survey of the design community, a recurring effort that dates back to 2007. Rich on statistics and loaded with information, it showed that SystemVerilog and UVM are now the preferred choices for electronic design automation. The entire set of slides is available on Harry’s blog available at the Verification Horizons Blog.

In an interesting twist, Harry overlaid the trends in the Indian design community to worldwide trends. It revealed India’s leadership position in using and adopting design languages and design methodologies such as formal verification, SystemVerilog, UVM, SystemVerilog assertions and Unified Power Format (UPF).

The keynote on the second day was delivered by Manoj Gandhi, Synopsys’ Executive Vice President and General Manager of the Verification Group. Titled “Propelling the Next Generation of Verification Innovation,” it started with a review of the characteristics of today designs, propelled by the upsurge of the Internet of Things (IoT). Smaller, faster and lower power devices stuffed with embedded software now are the de facto features of modern SoC designs. After a series of thought-provoking slides stuffed with market data, the presentation turned into a marketing pitch for Synopsys’ Continuum verification environment and its emulation platform based on commercial FPGA devices.

I enjoyed a brief chuckle on a snub about my writings on emulation said by Mr. Gandhi to be outdated and not reflecting the latest capabilities of off-the-shelf FPGA-based emulation systems.

Two invited keynotes were a highlight. The first by Vinay Shenoy, Managing Director of Infineon Technologies India Pvt. Ltd., was titled, “Make in India, Implies Innovate-Engineer-Manufacture.” Atul Bhatia, Founder and Former CEO of nSys, offered a look at “Opportunities for Semiconductor Design Startups in India.” Both focused on the Indian startup landscape, providing advice for would-be entrepreneurs for funding and ways to bootstrap and drive a company to success.

The two-day event was stuffed with eight tutorials and 39 technical sessions on various aspects of design and design verification. I attended and enjoyed four of them, including one on testbench methodologies and a case study by nVidia on mapping its Tegra Application Processor (AP) on an FPGA prototype platform. I was pleased by the technical content and delivery style of the presenters.

A series of informative posters enlightened attendees on design flows covering UVM, assertion-based verification (ABV), formal verification, hardware/software co-verification and so much more.

The event included three panel discussions. I had the opportunity to moderate one of them, titled “Supporting the Evolving Verification Flow.” Panelists were Manish Singh, FrontEnd CAD director at Qualcomm, Mike Bartley, President and CEO of TVS, and Sanjay Gupta, Group Director at Mentor Graphics. I posed four questions on how to cope with the rise in embedded software in modern SoC designs, hardware emulation adoption, power analysis and estimation. The panelists engaged on all four questions and provided extensive and exhaustive responses. A questioner from the audience asked whether formal analysis is on the way out, possibly replaced by emulation. All three panelists vigorously rejected the idea, asserting that formal is here to stay and one of the critical verification engines.

DVCon India is a jewel in Accellera’s crown and one of three yearly conferences organized by the standards group. Another jewel is DVCon Europe coming to Munich, Germany, November 11-12. The centerpiece jewel, perhaps, is DVCon held each year in San Jose, Calif. Next year’s conference will be held February 29-March 3. While paper session submissions have closed, there’s still time to submit a tutorial or panel session proposal. Registration will open in early 2016.

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