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Gabe Moretti
Gabe Moretti
Mr. Moretti’s engineering career started in July 1968 at TRW Microelectronics laboratory where he developed one of the first logic simulators for the semiconductors industry. His carrier included working at Intel, Signetics (part of Philips NV), Chancellor Computers, and VeriBest (Intergraph) … More »

DVCon US 2018 is Bigger and Better

February 1st, 2018 by Gabe Moretti

During the last week of February, the DoubleTree hotel in San Jose, California will once again host DVCon U.S. Dennis Brophy, this year’s General Chair, refers to DVCon U.S. as being “bigger and better”. How much longer the conference can squeeze into these premises is a challenging topic for Accellera Systems Initiative, the conference sponsor since the turn of the century.

Dennis remembers the humble beginnings of this event in 1988. To disguise his age or maybe to underlie his seniority he claims not to remember attending it, but I know he was there. Much has happened since then in our industry, and much has changed. DVCon has changed and grown with the industry and it is now a truly world-wide institution with conferences occurring also in Europe, India, and China.

DVCon has followed closely the changing realities of the electronics industry. From a place to learn about new Hardware Description Languages to one where you can attend a session about Big Data and autonomous automobiles, for example. From just three workshops presented by the leading companies in EDA to an entire day of workshops that will parallel the tutorial sessions. But let me go in order.
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DAC 2011 Trip Reports – Mostly Transistor Level Tools

June 17th, 2011 by Daniel Payne

2011 was the year of the foundry (TSMC, Globalfoundries, Samsung) at DAC in San Diego. The foundries had bigger booths, bigger events, were on more panel sessions, and had more marketing influence than any other year that I can remember.

The attendance numbers from EDAC suggest a modest increase in EDA vendors and total attendees for 2011 compared to 2010, ironically the EDAC web site doesn’t even have their own Press Release posted yet after 8 days (did you all go on vacation after DAC?).

Enjoy reading my trip reports.

Read the rest of DAC 2011 Trip Reports – Mostly Transistor Level Tools

3D Extraction at DAC in San Diego

May 24th, 2011 by Daniel Payne

I’ve organized a pavilion panel session, “3D Extraction: Coming to a Design Near You?“. This panel is on Tuesday, June 7 at 3:00PM, booth #3421.

Our moderator is Andrew Kahng (UC San Diego), and panelists: Carey Robertson (Mentor Graphics), Ji Zheng (Apache DA), and Sourav Chakravarty (Intel).

Andrew Kahng Carey Robertson Ji Zheng Sourav Chakravarty

What Can a Wiki do for EDA?

January 23rd, 2011 by Daniel Payne

screen-shot-2011-01-23-at-71724-pmFellow EDA blogger Daniel Nenni has introduced me to the concept of the Wiki applied to EDA. So, just what is a Wiki?

Well, according to wikipedia:

A wiki (play /ˈwɪki/ WIK-ee) is a website that allows the creation and editing of any number of interlinked web pages via a web browser using a simplified markup language or a WYSIWYG text editor.

Daniel Nenni, PaulMcLellan, Eric Esteve and I have joined forces to blog about the EDA and semiconductor IP industry over at

We’ve organized wikis by:

Let’s say that you were interested to see and contribute to the list of all known EDA mergers and acquisitions since 1985, there’s a Wiki page just for that. Read it, contribute to it, tell your EDA colleagues about it.

screen-shot-2011-01-23-at-72718-pmMentor Graphics has a Wiki page just about their history since 1982, it’s a fun place to reminisce and then add your thoughts.

There’s nothing else quite like SemiWiki and we hope to see you visit and register today.

EDA Networking in Oregon this Friday, 5:30PM-7PM

July 7th, 2010 by Daniel Payne

Friday networking

July 9th, 2010
5:30PM – 7PM (not lunch time, but drinks and finger food after work)

Olive Garden Restaurant, Lake Oswego.

Discussion Ideas

· DAC Conference, attendance down 25% so does it matter?

· Carl Icahn is still after Mentor Graphics

· Would you take an RF EDA survey for an MBA project? Contact Stella Mandehou on LinkedIn

· Cadence touts EDA360, watch the video, read the white paper, drink the cool aid

· Coolest new feature on LinkedIn is to follow companies, see who joined, who left, what jobs are open

Bring business cards and enjoy networking.

My DAC Trip Report for 2010

June 17th, 2010 by Daniel Payne
  1. Photo tour on Sunday
  2. Enabling IR drop analysis for IC designs using a macro model for the power and ground network
  3. 3D field solver for IC designs uses a mesh technique
  4. Analog IC designs can be optimized and made portable
  5. Monte Carlo for SPICE and FastSPICE get faster and smarter
  6. SPICE and FastSPICE tools get faster
  7. SPICE, FastSPICE and rail analysis
  8. AMS users talk about success and issues with SPICE and FastSPICE
  9. Analog FastSPICE goes parallel
  10. A new way to do DRC using a windowed approach
  11. Variation aware IC design for 45nm and smaller
  12. 3D extraction for IC designs gives best accuracy
  13. Speeding ASIC designs with cells optimized on the fly
  14. OpenPDK or iPDK or both?
  15. SPICE and FastSPICE from Legend
  16. Another parallel SPICE simulator
  17. ESD integrity
  18. Coolest car
  19. How to draw a crowd

Anaheim Convention Center

Anaheim Convention Center

SPICE Circuit Simulation at DAC 2010

May 20th, 2010 by Daniel Payne

Hot and SPICEy: Users Review Different Flavors of SPICE and Fast SPICE

Topic Area: Analog/Mixed-Signal/RF Design

Tuesday, June 15, 2010
Time: 4:30 PM — 5:15 PM
Location: Booth #694


Are you one of the 20,000 analog and mixed-signal designers stuck waiting for your SPICE simulation run to complete today? Inexpensive multi-core hardware, multi-threaded software, and new algorithms promise to deliver SPICE accuracy 10- to 100-times faster than earlier methods. The panelists have evaluated the new generation of fast SPICE products and will discuss the trad-eoffs of each approach from a users’ perspective.

Click here to view Pavilion Panel videos.

Chair: Daniel Payne – Marketing EDA, Tualatin, OR
Organizer: Daniel Payne – Marketing EDA, Tualatin, OR
Speakers: Aaron Barker – Oracle, Broomfield, CO
Pierluigi Daglio – STMicroelectronics, Agrate, Italy
Jin-Qin Lu – Atheros Communications, Inc., Santa Clara, CA

What is New with SPICE?

March 17th, 2010 by Daniel Payne

I thought this would be a great topic for a panel discussion at DAC and will be moderating a panel session in the Pavilion on Tuesday, June 15th at 4:30PM.

This panel will not have any EDA vendors, instead it will have EDA users from: Atheros, Sun Microsystems and STMicroelectronics.

See the list of questions that I have for discussion, and please post your favorite questions here and I’ll add them to the mix.

Bye, Bye Gemini

February 19th, 2010 by Daniel Payne

I’ve blogged about Gemini before:

In December 2009 I first heard that Gemini DA was in play by my Silicon Valley sources, then today we read in Cooley’s ESNUG that redirects to

Their tool was yet another Parallel FastSPICE circuit simulator.

Evidently it wasn’t selling enough or different enough from the other commercial tools being offered.

I love to see the little guy shake up the marketplace, although in this case it appears that Synopsys has acquired the technology with little fanfare.

Carbon Footprint is Good For ICs

February 16th, 2010 by Daniel Payne

IBM just demonstrated graphene transistors that could become a replacement for pure silicon-based ICs.

Photo: Courtesy of IBM, posted at EE Times

The demonstration showed 100GHz operation at room temperature with a production goal of 1THz.

This is funded by DARPA the folks who really created the Internet.

We need to add Silicon-Carbide (SiC) to our vocabulary.

I’ll never forget the transition from NMOS technology to CMOS technology. When I was doing DRAM designs the performance was limited by the power dissipation on the chip and the ability of the ceramic or plastic packages to conduct heat away from the chip. Higher temperatures would slow down chip speeds.

CMOS came to the rescue and provided a much lower standby and switching power characteristics.

Today, we’re at a similar inflection point, hoping that something new will replace bulk CMOS transistors that will allow billions of transistors at a reasonable cost and run on batteries.

TrueCircuits: IoTPLL

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